sar 39 arch/mips/include/asm/txx9/tx3927.h volatile unsigned long sar; sar 121 arch/parisc/include/asm/asmregs.h sar: .reg %cr11 sar 285 arch/parisc/include/asm/elf.h dst[44] = pt->sar; dst[45] = pt->iir; \ sar 31 arch/parisc/include/asm/kgdb.h unsigned long sar; sar 35 arch/parisc/include/uapi/asm/ptrace.h unsigned long sar; /* CR11 */ sar 56 arch/parisc/include/uapi/asm/ptrace.h unsigned long sar; /* CR11 */ sar 134 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_SAR, offsetof(struct task_struct, thread.regs.sar)); sar 223 arch/parisc/kernel/asm-offsets.c DEFINE(PT_SAR, offsetof(struct pt_regs, sar)); sar 80 arch/parisc/kernel/kgdb.c gr->sar = regs->sar; sar 111 arch/parisc/kernel/kgdb.c regs->sar = gr->sar; sar 464 arch/parisc/kernel/ptrace.c case RI(sar): return regs->sar; sar 510 arch/parisc/kernel/ptrace.c case RI(sar): regs->sar = val; sar 762 arch/parisc/kernel/ptrace.c REG_OFFSET_NAME(sar), sar 80 arch/parisc/kernel/signal.c err |= __get_user(regs->sar, &sc->sc_sar); sar 221 arch/parisc/kernel/signal.c err |= __put_user(regs->sar, &sc->sc_sar); sar 100 arch/parisc/kernel/signal32.c regs->sar = ((u64)compat_regt << 32) | (u64)compat_reg; sar 102 arch/parisc/kernel/signal32.c DBG(2,"restore_sigcontext32: sar is %#lx\n", regs->sar); sar 238 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->sar); sar 242 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->sar >> 32); sar 368 arch/parisc/kernel/traps.c regs->sar = pim_wide->cr[11]; sar 392 arch/parisc/kernel/traps.c regs->sar = pim_narrow->cr[11]; sar 288 arch/sh/drivers/dma/dma-api.c channel->sar = from; sar 97 arch/sh/drivers/dma/dma-g2.c if (chan->sar & 31) { sar 98 arch/sh/drivers/dma/dma-g2.c printk("g2dma: unaligned source 0x%lx\n", chan->sar); sar 117 arch/sh/drivers/dma/dma-g2.c flush_icache_range((unsigned long)chan->sar, chan->count); sar 122 arch/sh/drivers/dma/dma-g2.c g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; sar 55 arch/sh/drivers/dma/dma-pvr2.c if (chan->sar || !chan->dar) sar 217 arch/sh/drivers/dma/dma-sh.c if (chan->sar || (mach_is_dreamcast() && sar 219 arch/sh/drivers/dma/dma-sh.c __raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR)); sar 72 arch/sh/include/asm/dma.h unsigned long sar; sar 1021 arch/x86/kvm/emulate.c FASTOP2CL(sar); sar 63 arch/xtensa/include/asm/ptrace.h unsigned long sar; /* 44 */ sar 49 arch/xtensa/include/uapi/asm/ptrace.h __u32 sar; sar 42 arch/xtensa/kernel/asm-offsets.c DEFINE(PT_SAR, offsetof (struct pt_regs, sar)); sar 51 arch/xtensa/kernel/ptrace.c .sar = regs->sar, sar 91 arch/xtensa/kernel/ptrace.c regs->sar = newregs.sar; sar 323 arch/xtensa/kernel/ptrace.c tmp = regs->sar; sar 146 arch/xtensa/kernel/signal.c COPY(sar); sar 185 arch/xtensa/kernel/signal.c COPY(sar); sar 473 arch/xtensa/kernel/traps.c regs->lbeg, regs->lend, regs->lcount, regs->sar); sar 45 drivers/clk/mvebu/armada-370.c static u32 __init a370_get_tclk_freq(void __iomem *sar) sar 49 drivers/clk/mvebu/armada-370.c tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & sar 64 drivers/clk/mvebu/armada-370.c static u32 __init a370_get_cpu_freq(void __iomem *sar) sar 69 drivers/clk/mvebu/armada-370.c cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & sar 114 drivers/clk/mvebu/armada-370.c void __iomem *sar, int id, int *mult, int *div) sar 116 drivers/clk/mvebu/armada-370.c u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & sar 135 drivers/clk/mvebu/armada-370.c static bool a370_is_sscg_enabled(void __iomem *sar) sar 137 drivers/clk/mvebu/armada-370.c return !(readl(sar) & SARL_A370_SSCG_ENABLE); sar 50 drivers/clk/mvebu/armada-375.c static u32 __init armada_375_get_tclk_freq(void __iomem *sar) sar 54 drivers/clk/mvebu/armada-375.c tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) & sar 71 drivers/clk/mvebu/armada-375.c static u32 __init armada_375_get_cpu_freq(void __iomem *sar) sar 75 drivers/clk/mvebu/armada-375.c cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & sar 115 drivers/clk/mvebu/armada-375.c void __iomem *sar, int id, int *mult, int *div) sar 117 drivers/clk/mvebu/armada-375.c u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & sar 37 drivers/clk/mvebu/armada-38x.c static u32 __init armada_38x_get_tclk_freq(void __iomem *sar) sar 41 drivers/clk/mvebu/armada-38x.c tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) & sar 54 drivers/clk/mvebu/armada-38x.c static u32 __init armada_38x_get_cpu_freq(void __iomem *sar) sar 58 drivers/clk/mvebu/armada-38x.c cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & sar 99 drivers/clk/mvebu/armada-38x.c void __iomem *sar, int id, int *mult, int *div) sar 101 drivers/clk/mvebu/armada-38x.c u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & sar 45 drivers/clk/mvebu/armada-39x.c static u32 __init armada_39x_get_tclk_freq(void __iomem *sar) sar 49 drivers/clk/mvebu/armada-39x.c tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & sar 68 drivers/clk/mvebu/armada-39x.c static u32 __init armada_39x_get_cpu_freq(void __iomem *sar) sar 72 drivers/clk/mvebu/armada-39x.c cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & sar 92 drivers/clk/mvebu/armada-39x.c void __iomem *sar, int id, int *mult, int *div) sar 110 drivers/clk/mvebu/armada-39x.c static u32 __init armada_39x_refclk_ratio(void __iomem *sar) sar 112 drivers/clk/mvebu/armada-39x.c if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ) sar 48 drivers/clk/mvebu/armada-xp.c static u32 __init axp_get_tclk_freq(void __iomem *sar) sar 54 drivers/clk/mvebu/armada-xp.c static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) sar 74 drivers/clk/mvebu/armada-xp.c static u32 __init axp_get_cpu_freq(void __iomem *sar) sar 79 drivers/clk/mvebu/armada-xp.c cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & sar 85 drivers/clk/mvebu/armada-xp.c cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & sar 97 drivers/clk/mvebu/armada-xp.c static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) sar 136 drivers/clk/mvebu/armada-xp.c void __iomem *sar, int id, int *mult, int *div) sar 138 drivers/clk/mvebu/armada-xp.c u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & sar 144 drivers/clk/mvebu/armada-xp.c opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & sar 28 drivers/clk/mvebu/common.h u32 (*get_tclk_freq)(void __iomem *sar); sar 29 drivers/clk/mvebu/common.h u32 (*get_cpu_freq)(void __iomem *sar); sar 30 drivers/clk/mvebu/common.h void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); sar 31 drivers/clk/mvebu/common.h u32 (*get_refclk_freq)(void __iomem *sar); sar 32 drivers/clk/mvebu/common.h bool (*is_sscg_enabled)(void __iomem *sar); sar 87 drivers/clk/mvebu/dove.c static u32 __init dove_get_tclk_freq(void __iomem *sar) sar 89 drivers/clk/mvebu/dove.c u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & sar 106 drivers/clk/mvebu/dove.c static u32 __init dove_get_cpu_freq(void __iomem *sar) sar 108 drivers/clk/mvebu/dove.c u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & sar 126 drivers/clk/mvebu/dove.c void __iomem *sar, int id, int *mult, int *div) sar 131 drivers/clk/mvebu/dove.c u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & sar 139 drivers/clk/mvebu/dove.c u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & sar 86 drivers/clk/mvebu/kirkwood.c static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) sar 88 drivers/clk/mvebu/kirkwood.c u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & sar 108 drivers/clk/mvebu/kirkwood.c static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) sar 110 drivers/clk/mvebu/kirkwood.c u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); sar 127 drivers/clk/mvebu/kirkwood.c void __iomem *sar, int id, int *mult, int *div) sar 132 drivers/clk/mvebu/kirkwood.c u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); sar 139 drivers/clk/mvebu/kirkwood.c u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & sar 155 drivers/clk/mvebu/kirkwood.c static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) sar 157 drivers/clk/mvebu/kirkwood.c u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; sar 167 drivers/clk/mvebu/kirkwood.c void __iomem *sar, int id, int *mult, int *div) sar 179 drivers/clk/mvebu/kirkwood.c u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & sar 188 drivers/clk/mvebu/kirkwood.c static u32 __init mv98dx1135_get_tclk_freq(void __iomem *sar) sar 44 drivers/clk/mvebu/mv98dx3236.c static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) sar 68 drivers/clk/mvebu/mv98dx3236.c static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) sar 73 drivers/clk/mvebu/mv98dx3236.c cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & sar 118 drivers/clk/mvebu/mv98dx3236.c void __iomem *sar, int id, int *mult, int *div) sar 120 drivers/clk/mvebu/mv98dx3236.c u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & sar 28 drivers/clk/mvebu/orion.c static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) sar 30 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & sar 45 drivers/clk/mvebu/orion.c static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) sar 47 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & sar 59 drivers/clk/mvebu/orion.c static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, sar 62 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & sar 98 drivers/clk/mvebu/orion.c static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar) sar 100 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & sar 113 drivers/clk/mvebu/orion.c static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar) sar 115 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & sar 127 drivers/clk/mvebu/orion.c static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id, sar 130 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & sar 163 drivers/clk/mvebu/orion.c static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar) sar 172 drivers/clk/mvebu/orion.c static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar) sar 174 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & sar 184 drivers/clk/mvebu/orion.c static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id, sar 187 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & sar 223 drivers/clk/mvebu/orion.c static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar) sar 225 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & sar 238 drivers/clk/mvebu/orion.c static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar) sar 240 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & sar 250 drivers/clk/mvebu/orion.c static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id, sar 253 drivers/clk/mvebu/orion.c u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & sar 392 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.sar = cpu_to_le64(adr); sar 525 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c le64_to_cpu(desc->lli.sar), sar 68 drivers/dma/dw-axi-dmac/dw-axi-dmac.h __le64 sar; sar 390 drivers/dma/dw-edma/dw-edma-core.c burst->sar = src_addr; sar 407 drivers/dma/dw-edma/dw-edma-core.c burst->sar = xfer->xfer.cyclic.paddr; sar 409 drivers/dma/dw-edma/dw-edma-core.c burst->sar = sg_dma_address(sg); sar 46 drivers/dma/dw-edma/dw-edma-core.h u64 sar; sar 216 drivers/dma/dw-edma/dw-edma-v0-core.c SET_LL(&lli[i].sar_low, lower_32_bits(child->sar)); sar 217 drivers/dma/dw-edma/dw-edma-v0-core.c SET_LL(&lli[i].sar_high, upper_32_bits(child->sar)); sar 168 drivers/dma/dw/core.c channel_writel(dwc, SAR, lli_read(desc, sar)); sar 421 drivers/dma/dw/core.c lli_read(desc, sar), sar 590 drivers/dma/dw/core.c lli_write(desc, sar, src + offset); sar 680 drivers/dma/dw/core.c lli_write(desc, sar, mem); sar 728 drivers/dma/dw/core.c lli_write(desc, sar, reg); sar 369 drivers/dma/dw/regs.h __le32 sar; sar 111 drivers/dma/fsldma.h u64 sar; /* 0x10 - Source Address Register */ sar 234 drivers/dma/idma64.c u64 sar, dar; sar 240 drivers/dma/idma64.c sar = hw->phys; sar 244 drivers/dma/idma64.c src_width = __ffs(sar | hw->len | 4); sar 247 drivers/dma/idma64.c sar = config->src_addr; sar 255 drivers/dma/idma64.c lli->sar = sar; sar 97 drivers/dma/idma64.h u64 sar; sar 49 drivers/dma/sh/rcar-dmac.c u32 sar; sar 734 drivers/dma/sh/rcar-dmac.c hwdesc->sar = chunk->src_addr; sar 45 drivers/dma/sh/shdma.h u32 sar; /* SAR / source address */ sar 217 drivers/dma/sh/shdmac.c sh_dmae_writel(sh_chan, hw->sar, SAR); sar 291 drivers/dma/sh/shdmac.c sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); sar 387 drivers/dma/sh/shdmac.c sh_desc->hw.sar = src; sar 466 drivers/dma/sh/shdmac.c (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); sar 1728 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c static inline int vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar) sar 1750 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c return t[sar]; sar 64 drivers/media/platform/sti/bdisp/bdisp-reg.h u32 sar; sar 289 include/net/bluetooth/bluetooth.h sar:2, sar 41 include/sound/sof/xtensa.h uint32_t sar; sar 933 net/bluetooth/l2cap_core.c control->sar = 0; sar 938 net/bluetooth/l2cap_core.c control->sar = (enh & L2CAP_CTRL_SAR) >> L2CAP_CTRL_SAR_SHIFT; sar 957 net/bluetooth/l2cap_core.c control->sar = 0; sar 962 net/bluetooth/l2cap_core.c control->sar = (ext & L2CAP_EXT_CTRL_SAR) >> L2CAP_EXT_CTRL_SAR_SHIFT; sar 996 net/bluetooth/l2cap_core.c packed |= control->sar << L2CAP_EXT_CTRL_SAR_SHIFT; sar 1015 net/bluetooth/l2cap_core.c packed |= control->sar << L2CAP_CTRL_SAR_SHIFT; sar 2321 net/bluetooth/l2cap_core.c u8 sar; sar 2347 net/bluetooth/l2cap_core.c sar = L2CAP_SAR_UNSEGMENTED; sar 2351 net/bluetooth/l2cap_core.c sar = L2CAP_SAR_START; sar 2363 net/bluetooth/l2cap_core.c bt_cb(skb)->l2cap.sar = sar; sar 2371 net/bluetooth/l2cap_core.c sar = L2CAP_SAR_END; sar 2374 net/bluetooth/l2cap_core.c sar = L2CAP_SAR_CONTINUE; sar 5909 net/bluetooth/l2cap_core.c switch (control->sar) { sar 6688 net/bluetooth/l2cap_core.c if (!control->sframe && control->sar == L2CAP_SAR_START) sar 6707 net/bluetooth/l2cap_core.c control->sar, control->reqseq, control->final, sar 717 sound/soc/fsl/fsl_dma.c position = in_be32(&dma_channel->sar); sar 785 sound/soc/fsl/fsl_dma.c out_be32(&dma_channel->sar, 0); sar 17 sound/soc/fsl/fsl_dma.h __be32 sar; /* Source address register */ sar 98 sound/soc/sof/xtensa/core.c xoops->exccause, xoops->excvaddr, xoops->ps, xoops->sar);