s4clk1 450 arch/mips/cavium-octeon/executive/cvmx-spi.c if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { s4clk1 458 arch/mips/cavium-octeon/executive/cvmx-spi.c stat.s.s4clk1 = 0; s4clk1 464 arch/mips/cavium-octeon/executive/cvmx-spi.c } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); s4clk1 119 arch/mips/include/asm/octeon/cvmx-spxx-defs.h uint64_t s4clk1:1; s4clk1 129 arch/mips/include/asm/octeon/cvmx-spxx-defs.h uint64_t s4clk1:1;