s4clk0            450 arch/mips/cavium-octeon/executive/cvmx-spi.c 		if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
s4clk0            457 arch/mips/cavium-octeon/executive/cvmx-spi.c 			stat.s.s4clk0 = 0;
s4clk0            464 arch/mips/cavium-octeon/executive/cvmx-spi.c 	} while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
s4clk0            120 arch/mips/include/asm/octeon/cvmx-spxx-defs.h 		uint64_t s4clk0:1;
s4clk0            128 arch/mips/include/asm/octeon/cvmx-spxx-defs.h 		uint64_t s4clk0:1;