SCL_TAP_CONTROL   131 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET_2(SCL_TAP_CONTROL, 0,
SCL_TAP_CONTROL    77 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_TAP_CONTROL, SCL, id), \
SCL_TAP_CONTROL   160 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
SCL_TAP_CONTROL   161 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
SCL_TAP_CONTROL   425 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t SCL_TAP_CONTROL;
SCL_TAP_CONTROL    61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_TAP_CONTROL, DSCL, id), \
SCL_TAP_CONTROL  1104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t SCL_TAP_CONTROL; \
SCL_TAP_CONTROL   569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_4(SCL_TAP_CONTROL, 0,
SCL_TAP_CONTROL   729 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_SET_4(SCL_TAP_CONTROL, 0,