SCL_MODE          125 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
SCL_MODE          127 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_UPDATE(SCL_MODE, SCL_MODE, 0);
SCL_MODE          136 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_MODE, 1);
SCL_MODE          138 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_MODE, 2);
SCL_MODE          141 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
SCL_MODE           76 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_MODE, SCL, id), \
SCL_MODE          159 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
SCL_MODE          205 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
SCL_MODE          252 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
SCL_MODE          341 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	type SCL_MODE; \
SCL_MODE          424 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t SCL_MODE;
SCL_MODE          179 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE);
SCL_MODE          183 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
SCL_MODE          194 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
SCL_MODE           56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_MODE, DSCL, id), \
SCL_MODE         1099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t SCL_MODE; \
SCL_MODE          354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			uint32_t scl_mode = REG_READ(SCL_MODE);
SCL_MODE          388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			REG_SET_2(SCL_MODE, scl_mode,
SCL_MODE          541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
SCL_MODE          700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);