SCL_COEF_RAM_TAP_DATA  222 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
SCL_COEF_RAM_TAP_DATA   85 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
SCL_COEF_RAM_TAP_DATA  171 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
SCL_COEF_RAM_TAP_DATA  172 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
SCL_COEF_RAM_TAP_DATA  173 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
SCL_COEF_RAM_TAP_DATA  174 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
SCL_COEF_RAM_TAP_DATA  435 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t SCL_COEF_RAM_TAP_DATA;
SCL_COEF_RAM_TAP_DATA   63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SCL_COEF_RAM_TAP_DATA 1106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t SCL_COEF_RAM_TAP_DATA; \
SCL_COEF_RAM_TAP_DATA  284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,