SCL_COEF_RAM_SELECT 210 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_SET_3(SCL_COEF_RAM_SELECT, 0, SCL_COEF_RAM_SELECT 84 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(SCL_COEF_RAM_SELECT, SCL, id), \ SCL_COEF_RAM_SELECT 168 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ SCL_COEF_RAM_SELECT 169 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ SCL_COEF_RAM_SELECT 170 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ SCL_COEF_RAM_SELECT 434 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h uint32_t SCL_COEF_RAM_SELECT; SCL_COEF_RAM_SELECT 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ SCL_COEF_RAM_SELECT 513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h type SCL_COEF_RAM_SELECT; \ SCL_COEF_RAM_SELECT 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_COEF_RAM_SELECT, !coef_ram_current,