SCL_BLACK_OFFSET   60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_BLACK_OFFSET, DSCL, id), \
SCL_BLACK_OFFSET 1103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t SCL_BLACK_OFFSET; \
SCL_BLACK_OFFSET  560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 		REG_SET_2(SCL_BLACK_OFFSET, 0,
SCL_BLACK_OFFSET  565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 		REG_SET_2(SCL_BLACK_OFFSET, 0,
SCL_BLACK_OFFSET  713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	if (REG(SCL_BLACK_OFFSET)) {
SCL_BLACK_OFFSET  715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			REG_SET_2(SCL_BLACK_OFFSET, 0,
SCL_BLACK_OFFSET  720 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 			REG_SET_2(SCL_BLACK_OFFSET, 0,