CLK1_CLK3_DS_CNTL  173 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);	//dcf deep sleep divider
CLK1_CLK3_DS_CNTL  198 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
CLK1_CLK3_DS_CNTL  265 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 					internal.CLK1_CLK3_DS_CNTL);
CLK1_CLK3_DS_CNTL  114 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	uint32_t CLK1_CLK3_DS_CNTL;		//dcf_deep_sleep_divider