rx_hash_fields_mask 603 drivers/infiniband/hw/mlx4/main.c resp.rss_caps.rx_hash_fields_mask = rx_hash_fields_mask 615 drivers/infiniband/hw/mlx4/main.c resp.rss_caps.rx_hash_fields_mask |= rx_hash_fields_mask 555 drivers/infiniband/hw/mlx4/qp.c if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | rx_hash_fields_mask 565 drivers/infiniband/hw/mlx4/qp.c ucmd->rx_hash_fields_mask); rx_hash_fields_mask 569 drivers/infiniband/hw/mlx4/qp.c if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && rx_hash_fields_mask 570 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { rx_hash_fields_mask 572 drivers/infiniband/hw/mlx4/qp.c } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || rx_hash_fields_mask 573 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { rx_hash_fields_mask 578 drivers/infiniband/hw/mlx4/qp.c if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && rx_hash_fields_mask 579 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { rx_hash_fields_mask 581 drivers/infiniband/hw/mlx4/qp.c } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || rx_hash_fields_mask 582 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { rx_hash_fields_mask 587 drivers/infiniband/hw/mlx4/qp.c if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && rx_hash_fields_mask 588 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { rx_hash_fields_mask 602 drivers/infiniband/hw/mlx4/qp.c } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || rx_hash_fields_mask 603 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { rx_hash_fields_mask 608 drivers/infiniband/hw/mlx4/qp.c if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && rx_hash_fields_mask 609 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { rx_hash_fields_mask 618 drivers/infiniband/hw/mlx4/qp.c } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || rx_hash_fields_mask 619 drivers/infiniband/hw/mlx4/qp.c (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { rx_hash_fields_mask 624 drivers/infiniband/hw/mlx4/qp.c if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { rx_hash_fields_mask 928 drivers/infiniband/hw/mlx5/main.c resp.rss_caps.rx_hash_fields_mask = rx_hash_fields_mask 940 drivers/infiniband/hw/mlx5/main.c resp.rss_caps.rx_hash_fields_mask |= rx_hash_fields_mask 1655 drivers/infiniband/hw/mlx5/qp.c if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && rx_hash_fields_mask 1699 drivers/infiniband/hw/mlx5/qp.c if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) rx_hash_fields_mask 1724 drivers/infiniband/hw/mlx5/qp.c if (!ucmd.rx_hash_fields_mask) { rx_hash_fields_mask 1732 drivers/infiniband/hw/mlx5/qp.c if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || rx_hash_fields_mask 1733 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && rx_hash_fields_mask 1734 drivers/infiniband/hw/mlx5/qp.c ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || rx_hash_fields_mask 1735 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { rx_hash_fields_mask 1741 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || rx_hash_fields_mask 1742 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) rx_hash_fields_mask 1745 drivers/infiniband/hw/mlx5/qp.c else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || rx_hash_fields_mask 1746 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) rx_hash_fields_mask 1750 drivers/infiniband/hw/mlx5/qp.c outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || rx_hash_fields_mask 1751 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | rx_hash_fields_mask 1752 drivers/infiniband/hw/mlx5/qp.c ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || rx_hash_fields_mask 1753 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | rx_hash_fields_mask 1754 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; rx_hash_fields_mask 1763 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || rx_hash_fields_mask 1764 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) rx_hash_fields_mask 1767 drivers/infiniband/hw/mlx5/qp.c else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || rx_hash_fields_mask 1768 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) rx_hash_fields_mask 1772 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || rx_hash_fields_mask 1773 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) rx_hash_fields_mask 1776 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || rx_hash_fields_mask 1777 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) rx_hash_fields_mask 1780 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || rx_hash_fields_mask 1781 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) rx_hash_fields_mask 1784 drivers/infiniband/hw/mlx5/qp.c if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || rx_hash_fields_mask 1785 drivers/infiniband/hw/mlx5/qp.c (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) rx_hash_fields_mask 1788 drivers/infiniband/hw/mlx5/qp.c if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) rx_hash_fields_mask 104 include/uapi/rdma/mlx4-abi.h __aligned_u64 rx_hash_fields_mask; /* Use enum mlx4_ib_rx_hash_fields */ rx_hash_fields_mask 164 include/uapi/rdma/mlx4-abi.h __aligned_u64 rx_hash_fields_mask; /* enum mlx4_ib_rx_hash_fields */ rx_hash_fields_mask 167 include/uapi/rdma/mlx5-abi.h __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ rx_hash_fields_mask 349 include/uapi/rdma/mlx5-abi.h __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */