rv_funcs          913 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.pp_smu.dm = ctx;
rv_funcs          914 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
rv_funcs          915 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
rv_funcs          916 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_display_count =
rv_funcs          918 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_min_deep_sleep_dcfclk =
rv_funcs          920 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_hard_min_dcfclk_by_freq =
rv_funcs          922 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_hard_min_fclk_by_freq =
rv_funcs         1507 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		pp = &dc->res_pool->pp_smu->rv_funcs;
rv_funcs          142 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	pp_smu = &clk_mgr->pp_smu->rv_funcs;
rv_funcs          232 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		pp_smu = &clk_mgr->pp_smu->rv_funcs;
rv_funcs         1425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
rv_funcs          296 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 		struct pp_smu_funcs_rv rv_funcs;