runl 18 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); runl 11 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h int runl; runl 152 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, runl 169 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wr32(device, 0x002274, (runl << 20) | nr); runl 172 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (!(nvkm_rd32(device, 0x002284 + (runl * 0x08)) & 0x00100000)) runl 175 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_error(subdev, "runlist %d update timeout\n", runl); runl 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_runlist_update(struct gk104_fifo *fifo, int runl) runl 189 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; runl 190 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->runlist[runl].next = !fifo->runlist[runl].next; runl 193 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { runl 197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { runl 205 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c func->commit(fifo, runl, mem, nr); runl 229 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_add_tail(&cgrp->head, &fifo->runlist[chan->runl].cgrp); runl 232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); runl 282 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int engn, runl; runl 300 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) runl 301 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_runlist_update(fifo, runl); runl 310 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_runl(struct gk104_fifo *fifo, int runl) runl 314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 runm = BIT(runl); runl 325 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl); runl 330 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_chid(struct gk104_fifo *fifo, int runl, int chid) runl 335 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { runl 342 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) { runl 362 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 runl = (stat & 0x000f0000) >> 16; runl 364 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c unsigned long engn, engm = fifo->runlist[runl].engm; runl 372 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c chan = gk104_fifo_recover_chid(fifo, runl, chid); runl 383 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_runl(fifo, runl); runl 401 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 runl = fifo->engine[engn].runl; runl 412 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_runl(fifo, runl); runl 759 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int runl = __ffs(mask); runl 760 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c wake_up(&fifo->runlist[runl].wait); runl 761 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wr32(device, 0x002a00, 1 << runl); runl 762 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mask &= ~(1 << runl); runl 884 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; runl 885 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (runl < fifo->runlist_nr) { runl 886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c unsigned long engm = fifo->runlist[runl].engm; runl 909 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int engn, runl, pbid, ret, i, j; runl 925 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { runl 928 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (map[j] & (1 << runl)) { runl 935 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c engn, runl, pbid, nvkm_subdev_name[engidx]); runl 938 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->engine[engn].runl = runl; runl 941 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->runlist[runl].engm |= 1 << engn; runl 942 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); runl 26 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h int runl; runl 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h void (*commit)(struct gk104_fifo *, int runl, runl 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h void gk104_fifo_runlist_update(struct gk104_fifo *, int runl); runl 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h void gk104_fifo_runlist_commit(struct gk104_fifo *, int runl, runl 195 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_runlist_update(fifo, chan->runl); runl 210 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16); runl 216 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_runlist_update(fifo, chan->runl); runl 272 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c chan->runl = runlist; runl 48 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl)); runl 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mask(device, 0x002630, BIT(chan->runl), 0); runl 152 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c chan->runl = runlist; runl 35 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c return (chan->runl << 16) | chan->base.chid; runl 32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl, runl 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr)); runl 40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr)); runl 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr); runl 143 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_engine(struct nvkm_device *device, int index, int *runl, int *engn) runl 151 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c *runl = info->runlist;