rq_regs_l         556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
rq_regs_l         557 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
rq_regs_l         558 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l         559 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
rq_regs_l         560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l         561 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
rq_regs_l         562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
rq_regs_l         563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
rq_regs_l        1027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
rq_regs_l        1028 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
rq_regs_l        1029 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l        1030 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
rq_regs_l        1031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l        1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
rq_regs_l        1033 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
rq_regs_l        1034 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
rq_regs_l         174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
rq_regs_l         175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l         176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l         177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
rq_regs_l         178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_l         213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
rq_regs_l         214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l         215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l         216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
rq_regs_l         217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_l         204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
rq_regs_l         205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
rq_regs_l         206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l         207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
rq_regs_l         208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l         209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
rq_regs_l         210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
rq_regs_l         211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
rq_regs_l        1225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
rq_regs_l        1226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
rq_regs_l        1227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l        1228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
rq_regs_l        1229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l        1230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
rq_regs_l        1231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
rq_regs_l        1232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
rq_regs_l         130 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
rq_regs_l         131 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
rq_regs_l         132 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs_l         133 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
rq_regs_l         134 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
rq_regs_l         135 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
rq_regs_l         136 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
rq_regs_l         137 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
rq_regs_l         196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
rq_regs_l         198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
rq_regs_l         207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
rq_regs_l         196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
rq_regs_l         198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
rq_regs_l         207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
rq_regs_l         175 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
rq_regs_l         177 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
rq_regs_l         188 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
rq_regs_l         495 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	display_data_rq_regs_st rq_regs_l;
rq_regs_l         183 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 	print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
rq_regs_l         239 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
rq_regs_l         243 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);