rq_regs_c         565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
rq_regs_c         566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c         567 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
rq_regs_c         568 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c         569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
rq_regs_c         570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c         571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
rq_regs_c         572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c        1037 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
rq_regs_c        1038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c        1039 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
rq_regs_c        1040 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c        1041 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
rq_regs_c        1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c        1043 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
rq_regs_c        1044 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c         178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c         179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c         180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c         181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c         217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c         218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c         219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c         220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c         213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
rq_regs_c         214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c         215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
rq_regs_c         216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c         217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
rq_regs_c         218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c         219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
rq_regs_c         220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c        1235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
rq_regs_c        1236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c        1237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
rq_regs_c        1238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c        1239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
rq_regs_c        1240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
rq_regs_c        1241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
rq_regs_c        1242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c         139 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
rq_regs_c         140 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
rq_regs_c         141 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
rq_regs_c         142 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs_c         143 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
rq_regs_c         144 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
rq_regs_c         145 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
rq_regs_c         202 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
rq_regs_c         203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
rq_regs_c         208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
rq_regs_c         202 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
rq_regs_c         203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
rq_regs_c         208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
rq_regs_c         182 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
rq_regs_c         183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(
rq_regs_c         189 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
rq_regs_c         496 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	display_data_rq_regs_st rq_regs_c;
rq_regs_c         185 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 	print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c);
rq_regs_c         241 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
rq_regs_c         244 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);