rq_regs 450 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; rq_regs 461 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c memset(rq_regs, 0, sizeof(*rq_regs)); rq_regs 495 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dml1_extract_rq_regs(dml, rq_regs, rq_param); rq_regs 544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs) rq_regs 549 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); rq_regs 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, rq_regs 552 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, rq_regs 553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, rq_regs 554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); rq_regs 556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, rq_regs 557 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, rq_regs 558 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, rq_regs 559 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs 560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, rq_regs 561 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, rq_regs 562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, rq_regs 563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); rq_regs 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, rq_regs 566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, rq_regs 567 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, rq_regs 568 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, rq_regs 570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, rq_regs 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, rq_regs 572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 668 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 674 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_requestor(hubp, rq_regs); rq_regs 852 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 856 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); rq_regs 858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, rq_regs 859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, rq_regs 860 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, rq_regs 861 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); rq_regs 1022 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 1027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, rq_regs 1028 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, rq_regs 1029 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, rq_regs 1030 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs 1031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, rq_regs 1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, rq_regs 1033 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, rq_regs 1034 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); rq_regs 1037 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, rq_regs 1038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, rq_regs 1039 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, rq_regs 1040 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 1041 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, rq_regs 1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, rq_regs 1043 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, rq_regs 1044 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct _vcs_dpi_display_rq_regs_st rq_regs; rq_regs 677 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct _vcs_dpi_display_rq_regs_st *rq_regs); rq_regs 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode, rq_regs 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, rq_regs 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, rq_regs 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, rq_regs 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, rq_regs 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size, rq_regs 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size, rq_regs 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 2326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->rq_regs, rq_regs 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode, rq_regs 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, rq_regs 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, rq_regs 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, rq_regs 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, rq_regs 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size, rq_regs 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size, rq_regs 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs) rq_regs 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); rq_regs 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, rq_regs 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, rq_regs 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, rq_regs 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); rq_regs 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, rq_regs 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, rq_regs 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, rq_regs 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, rq_regs 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, rq_regs 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, rq_regs 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); rq_regs 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, rq_regs 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, rq_regs 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, rq_regs 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, rq_regs 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, rq_regs 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, rq_regs 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_requestor(hubp, rq_regs); rq_regs 1050 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 1054 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); rq_regs 1056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, rq_regs 1057 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, rq_regs 1058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, rq_regs 1059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); rq_regs 1220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; rq_regs 1225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, rq_regs 1226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, rq_regs 1227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, rq_regs 1228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs 1229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, rq_regs 1230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, rq_regs 1231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, rq_regs 1232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); rq_regs 1235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, rq_regs 1236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, rq_regs 1237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, rq_regs 1238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 1239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, rq_regs 1240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, rq_regs 1241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, rq_regs 1242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 1348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->rq_regs, rq_regs 2832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &context->res_ctx.pipe_ctx[i].rq_regs, rq_regs 118 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs) rq_regs 123 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); rq_regs 125 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, rq_regs 126 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, rq_regs 127 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, rq_regs 128 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); rq_regs 130 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, rq_regs 131 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, rq_regs 132 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, rq_regs 133 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs 134 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, rq_regs 135 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, rq_regs 136 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, rq_regs 137 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); rq_regs 139 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, rq_regs 140 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, rq_regs 141 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, rq_regs 142 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs 143 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, rq_regs 144 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, rq_regs 145 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); rq_regs 152 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 160 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21_program_requestor(hubp, rq_regs); rq_regs 132 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct _vcs_dpi_display_rq_regs_st *rq_regs); rq_regs 166 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_data_rq_regs_st *rq_regs, rq_regs 172 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; rq_regs 175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_chunk_size = 0; rq_regs 177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; rq_regs 179 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; rq_regs 181 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_meta_chunk_size = 0; rq_regs 183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; rq_regs 185 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; rq_regs 186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; rq_regs 190 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_rq_regs_st *rq_regs, rq_regs 196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); rq_regs 198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), rq_regs 202 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); rq_regs 203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), rq_regs 207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); rq_regs 208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); rq_regs 213 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->drq_expansion_mode = 0; rq_regs 215 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->drq_expansion_mode = 2; rq_regs 217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->prq_expansion_mode = 1; rq_regs 218 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->mrq_expansion_mode = 1; rq_regs 219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->crq_expansion_mode = 1; rq_regs 231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->plane1_base_address = detile_buf_plane1_addr; rq_regs 752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_rq_regs_st *rq_regs, rq_regs 757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c memset(rq_regs, 0, sizeof(*rq_regs)); rq_regs 759 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c extract_rq_regs(mode_lib, rq_regs, rq_param); rq_regs 761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c print__rq_regs_st(mode_lib, *rq_regs); rq_regs 46 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h display_rq_regs_st *rq_regs, rq_regs 166 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_data_rq_regs_st *rq_regs, rq_regs 172 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; rq_regs 175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_chunk_size = 0; rq_regs 177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; rq_regs 179 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; rq_regs 181 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_meta_chunk_size = 0; rq_regs 183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; rq_regs 185 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; rq_regs 186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; rq_regs 190 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_rq_regs_st *rq_regs, rq_regs 196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); rq_regs 198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), rq_regs 202 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); rq_regs 203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), rq_regs 207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); rq_regs 208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); rq_regs 213 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->drq_expansion_mode = 0; rq_regs 215 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->drq_expansion_mode = 2; rq_regs 217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->prq_expansion_mode = 1; rq_regs 218 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->mrq_expansion_mode = 1; rq_regs 219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->crq_expansion_mode = 1; rq_regs 231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->plane1_base_address = detile_buf_plane1_addr; rq_regs 752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_rq_regs_st *rq_regs, rq_regs 757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c memset(rq_regs, 0, sizeof(*rq_regs)); rq_regs 759 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c extract_rq_regs(mode_lib, rq_regs, rq_param); rq_regs 761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c print__rq_regs_st(mode_lib, *rq_regs); rq_regs 46 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h display_rq_regs_st *rq_regs, rq_regs 144 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_data_rq_regs_st *rq_regs, rq_regs 150 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; rq_regs 153 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_chunk_size = 0; rq_regs 155 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; rq_regs 157 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; rq_regs 159 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_meta_chunk_size = 0; rq_regs 161 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; rq_regs 163 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; rq_regs 164 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; rq_regs 169 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_rq_regs_st *rq_regs, rq_regs 175 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); rq_regs 177 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( rq_regs 182 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); rq_regs 183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( rq_regs 188 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); rq_regs 189 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); rq_regs 194 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->drq_expansion_mode = 0; rq_regs 196 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->drq_expansion_mode = 2; rq_regs 198 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->prq_expansion_mode = 1; rq_regs 199 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->mrq_expansion_mode = 1; rq_regs 200 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->crq_expansion_mode = 1; rq_regs 213 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->plane1_base_address = detile_buf_plane1_addr; rq_regs 798 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_rq_regs_st *rq_regs, rq_regs 803 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c memset(rq_regs, 0, sizeof(*rq_regs)); rq_regs 805 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c extract_rq_regs(mode_lib, rq_regs, rq_param); rq_regs 807 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c print__rq_regs_st(mode_lib, *rq_regs); rq_regs 46 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h display_rq_regs_st *rq_regs, rq_regs 63 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h display_rq_regs_st *rq_regs, rq_regs 159 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs) rq_regs 163 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs.chunk_size); rq_regs 164 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size); rq_regs 165 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs.meta_chunk_size); rq_regs 168 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_regs.min_meta_chunk_size); rq_regs 169 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs.dpte_group_size); rq_regs 170 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs.mpte_group_size); rq_regs 171 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height); rq_regs 174 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_regs.pte_row_height_linear); rq_regs 178 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs) rq_regs 183 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l); rq_regs 185 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c); rq_regs 186 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x\n", rq_regs.drq_expansion_mode); rq_regs 187 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x\n", rq_regs.prq_expansion_mode); rq_regs 188 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x\n", rq_regs.mrq_expansion_mode); rq_regs 189 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x\n", rq_regs.crq_expansion_mode); rq_regs 190 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address); rq_regs 43 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs); rq_regs 208 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c struct _vcs_dpi_display_data_rq_regs_st *rq_regs, rq_regs 214 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; rq_regs 217 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_chunk_size = 0; rq_regs 219 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; rq_regs 221 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; rq_regs 223 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_meta_chunk_size = 0; rq_regs 225 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; rq_regs 227 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; rq_regs 228 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; rq_regs 233 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 239 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); rq_regs 241 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); rq_regs 243 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); rq_regs 244 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); rq_regs 250 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->drq_expansion_mode = 0; rq_regs 252 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->drq_expansion_mode = 2; rq_regs 254 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->prq_expansion_mode = 1; rq_regs 255 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->mrq_expansion_mode = 1; rq_regs 256 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->crq_expansion_mode = 1; rq_regs 269 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->plane1_base_address = detile_buf_plane1_addr; rq_regs 37 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 309 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct _vcs_dpi_display_rq_regs_st rq_regs; rq_regs 73 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct _vcs_dpi_display_rq_regs_st *rq_regs, rq_regs 97 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h struct _vcs_dpi_display_rq_regs_st *rq_regs,