rq_dlg_param 52 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 317 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) rq_dlg_param 450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; rq_dlg_param 452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) rq_dlg_param 454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; rq_dlg_param 458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height rq_dlg_param 461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width rq_dlg_param 488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; rq_dlg_param 493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; rq_dlg_param 495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; rq_dlg_param 497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; rq_dlg_param 524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; rq_dlg_param 542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; rq_dlg_param 544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; rq_dlg_param 611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; rq_dlg_param 630 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request rq_dlg_param 632 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request rq_dlg_param 634 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 662 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, rq_dlg_param 668 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 706 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_dlg_param, rq_dlg_param 772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 987 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; rq_dlg_param 989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; rq_dlg_param 994 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; rq_dlg_param 996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; rq_dlg_param 998 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; rq_dlg_param 999 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; rq_dlg_param 1128 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; rq_dlg_param 1129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; rq_dlg_param 1130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; rq_dlg_param 1131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; rq_dlg_param 1136 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; rq_dlg_param 1137 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; rq_dlg_param 52 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 317 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) rq_dlg_param 450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; rq_dlg_param 452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) rq_dlg_param 454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; rq_dlg_param 458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height rq_dlg_param 461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width rq_dlg_param 488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; rq_dlg_param 493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; rq_dlg_param 495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; rq_dlg_param 497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; rq_dlg_param 524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; rq_dlg_param 542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; rq_dlg_param 544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; rq_dlg_param 611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; rq_dlg_param 630 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request rq_dlg_param 632 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request rq_dlg_param 634 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 662 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, rq_dlg_param 668 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 706 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_dlg_param, rq_dlg_param 772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 987 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; rq_dlg_param 989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; rq_dlg_param 994 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; rq_dlg_param 996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; rq_dlg_param 998 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; rq_dlg_param 999 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; rq_dlg_param 1128 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; rq_dlg_param 1129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; rq_dlg_param 1130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; rq_dlg_param 1131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; rq_dlg_param 1136 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; rq_dlg_param 1137 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; rq_dlg_param 305 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 441 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) rq_dlg_param 443 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; rq_dlg_param 445 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->swath_width_ub = dml_round_to_multiple( rq_dlg_param 449 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; rq_dlg_param 453 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height rq_dlg_param 456 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width rq_dlg_param 483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; rq_dlg_param 488 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; rq_dlg_param 490 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; rq_dlg_param 492 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; rq_dlg_param 520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; rq_dlg_param 540 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; rq_dlg_param 542 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; rq_dlg_param 614 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 629 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; rq_dlg_param 633 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request rq_dlg_param 635 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request rq_dlg_param 637 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 670 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( rq_dlg_param 678 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 747 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_dlg_param, rq_dlg_param 819 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 1033 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; rq_dlg_param 1034 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; rq_dlg_param 1035 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; rq_dlg_param 1036 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; rq_dlg_param 1038 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; rq_dlg_param 1039 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; rq_dlg_param 1180 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; rq_dlg_param 1181 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; rq_dlg_param 1182 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; rq_dlg_param 1183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; rq_dlg_param 1188 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; rq_dlg_param 1189 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; rq_dlg_param 65 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param) rq_dlg_param 71 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.swath_width_ub); rq_dlg_param 74 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.swath_height); rq_dlg_param 77 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.req_per_swath_ub); rq_dlg_param 80 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.meta_pte_bytes_per_frame_ub); rq_dlg_param 83 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.dpte_req_per_row_ub); rq_dlg_param 86 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.dpte_groups_per_row_ub); rq_dlg_param 89 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.dpte_row_height); rq_dlg_param 92 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.dpte_bytes_per_row_ub); rq_dlg_param 95 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.meta_chunks_per_row_ub); rq_dlg_param 98 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.meta_req_per_row_ub); rq_dlg_param 101 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.meta_row_height); rq_dlg_param 104 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c rq_dlg_param.meta_bytes_per_row_ub); rq_dlg_param 125 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param) rq_dlg_param 130 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l); rq_dlg_param 132 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c); rq_dlg_param 37 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param); rq_dlg_param 39 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param); rq_dlg_param 539 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param, rq_dlg_param 676 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) rq_dlg_param 678 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; rq_dlg_param 680 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->swath_width_ub = dml_round_to_multiple( rq_dlg_param 684 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; rq_dlg_param 688 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height rq_dlg_param 691 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width rq_dlg_param 720 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; rq_dlg_param 725 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; rq_dlg_param 727 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; rq_dlg_param 755 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; rq_dlg_param 769 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; rq_dlg_param 771 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; rq_dlg_param 773 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; rq_dlg_param 841 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 850 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 857 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; rq_dlg_param 864 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; rq_dlg_param 866 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 868 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; rq_dlg_param 878 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; rq_dlg_param 905 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( rq_dlg_param 925 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (rq_dlg_param->meta_row_height != func_meta_row_height) { rq_dlg_param 928 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->meta_row_height); rq_dlg_param 933 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (rq_dlg_param->dpte_row_height != func_dpte_row_height) { rq_dlg_param 936 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_dlg_param->dpte_row_height); rq_dlg_param 983 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param, rq_dlg_param 1212 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c swath_height_l = rq_dlg_param.rq_l.swath_height; rq_dlg_param 1213 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; rq_dlg_param 1214 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; rq_dlg_param 1215 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; rq_dlg_param 1216 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; rq_dlg_param 1217 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; rq_dlg_param 1219 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c swath_height_c = rq_dlg_param.rq_c.swath_height; rq_dlg_param 1220 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; rq_dlg_param 1221 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; rq_dlg_param 1222 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; rq_dlg_param 1224 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; rq_dlg_param 1535 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; rq_dlg_param 1536 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; rq_dlg_param 1537 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; rq_dlg_param 1542 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; rq_dlg_param 1543 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; rq_dlg_param 60 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,