rps 934 drivers/block/floppy.c if (UDP->rps) { rps 937 drivers/block/floppy.c delta = ((delta * UDP->rps) % HZ) / UDP->rps; rps 3612 drivers/block/floppy.c unsigned char rps; rps 3744 drivers/block/floppy.c UDP->rps = v.rps; rps 3774 drivers/block/floppy.c v.rps = UDP->rps; rps 62 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps = dev_id; rps 64 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); rps 66 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.event_handler(&rps->clkevent); rps 71 drivers/clocksource/timer-oxnas-rps.c static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps, rps 75 drivers/clocksource/timer-oxnas-rps.c uint32_t cfg = rps->timer_prescaler; rps 83 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG); rps 84 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG); rps 89 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps = rps 92 drivers/clocksource/timer-oxnas-rps.c oxnas_rps_timer_config(rps, 0, 0); rps 99 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps = rps 102 drivers/clocksource/timer-oxnas-rps.c oxnas_rps_timer_config(rps, rps->timer_period, 1); rps 109 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps = rps 112 drivers/clocksource/timer-oxnas-rps.c oxnas_rps_timer_config(rps, rps->timer_period, 0); rps 120 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps = rps 123 drivers/clocksource/timer-oxnas-rps.c oxnas_rps_timer_config(rps, delta, 0); rps 128 drivers/clocksource/timer-oxnas-rps.c static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps) rps 130 drivers/clocksource/timer-oxnas-rps.c ulong clk_rate = clk_get_rate(rps->clk); rps 134 drivers/clocksource/timer-oxnas-rps.c rps->timer_prescaler = TIMER_DIV1; rps 135 drivers/clocksource/timer-oxnas-rps.c rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); rps 138 drivers/clocksource/timer-oxnas-rps.c if (rps->timer_period > TIMER_MAX_VAL) { rps 139 drivers/clocksource/timer-oxnas-rps.c rps->timer_prescaler = TIMER_DIV16; rps 141 drivers/clocksource/timer-oxnas-rps.c rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); rps 143 drivers/clocksource/timer-oxnas-rps.c if (rps->timer_period > TIMER_MAX_VAL) { rps 144 drivers/clocksource/timer-oxnas-rps.c rps->timer_prescaler = TIMER_DIV256; rps 146 drivers/clocksource/timer-oxnas-rps.c rps->timer_period = DIV_ROUND_UP(timer_rate, HZ); rps 149 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.name = "oxnas-rps"; rps 150 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC | rps 153 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.tick_resume = oxnas_rps_timer_shutdown; rps 154 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown; rps 155 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic; rps 156 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot; rps 157 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.set_next_event = oxnas_rps_timer_next_event; rps 158 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.rating = 200; rps 159 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.cpumask = cpu_possible_mask; rps 160 drivers/clocksource/timer-oxnas-rps.c rps->clkevent.irq = rps->irq; rps 161 drivers/clocksource/timer-oxnas-rps.c clockevents_config_and_register(&rps->clkevent, rps 168 drivers/clocksource/timer-oxnas-rps.c rps->timer_prescaler, rps 169 drivers/clocksource/timer-oxnas-rps.c rps->timer_period); rps 183 drivers/clocksource/timer-oxnas-rps.c static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps) rps 185 drivers/clocksource/timer-oxnas-rps.c ulong clk_rate = clk_get_rate(rps->clk); rps 191 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG); rps 193 drivers/clocksource/timer-oxnas-rps.c rps->clksrc_base + TIMER_CTRL_REG); rps 195 drivers/clocksource/timer-oxnas-rps.c timer_sched_base = rps->clksrc_base + TIMER_CURR_REG; rps 214 drivers/clocksource/timer-oxnas-rps.c struct oxnas_rps_timer *rps; rps 218 drivers/clocksource/timer-oxnas-rps.c rps = kzalloc(sizeof(*rps), GFP_KERNEL); rps 219 drivers/clocksource/timer-oxnas-rps.c if (!rps) rps 222 drivers/clocksource/timer-oxnas-rps.c rps->clk = of_clk_get(np, 0); rps 223 drivers/clocksource/timer-oxnas-rps.c if (IS_ERR(rps->clk)) { rps 224 drivers/clocksource/timer-oxnas-rps.c ret = PTR_ERR(rps->clk); rps 228 drivers/clocksource/timer-oxnas-rps.c ret = clk_prepare_enable(rps->clk); rps 238 drivers/clocksource/timer-oxnas-rps.c rps->irq = irq_of_parse_and_map(np, 0); rps 239 drivers/clocksource/timer-oxnas-rps.c if (rps->irq < 0) { rps 244 drivers/clocksource/timer-oxnas-rps.c rps->clkevt_base = base + TIMER1_REG_OFFSET; rps 245 drivers/clocksource/timer-oxnas-rps.c rps->clksrc_base = base + TIMER2_REG_OFFSET; rps 248 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG); rps 249 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG); rps 250 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG); rps 251 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG); rps 252 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG); rps 253 drivers/clocksource/timer-oxnas-rps.c writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG); rps 255 drivers/clocksource/timer-oxnas-rps.c ret = request_irq(rps->irq, oxnas_rps_timer_irq, rps 257 drivers/clocksource/timer-oxnas-rps.c "rps-timer", rps); rps 261 drivers/clocksource/timer-oxnas-rps.c ret = oxnas_rps_clocksource_init(rps); rps 265 drivers/clocksource/timer-oxnas-rps.c ret = oxnas_rps_clockevent_init(rps); rps 272 drivers/clocksource/timer-oxnas-rps.c free_irq(rps->irq, rps); rps 276 drivers/clocksource/timer-oxnas-rps.c clk_disable_unprepare(rps->clk); rps 278 drivers/clocksource/timer-oxnas-rps.c clk_put(rps->clk); rps 280 drivers/clocksource/timer-oxnas-rps.c kfree(rps); rps 106 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c struct amdgpu_ps *rps) rps 109 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (rps == adev->pm.dpm.current_ps) rps 111 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (rps == adev->pm.dpm.requested_ps) rps 113 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (rps == adev->pm.dpm.boot_ps) rps 337 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ rps 338 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) rps 495 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h struct amdgpu_ps *rps); rps 370 drivers/gpu/drm/amd/amdgpu/kv_dpm.c static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps) rps 372 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *ps = rps->ps_priv; rps 1223 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps) rps 1225 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *new_ps = kv_get_ps(rps); rps 1228 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->current_rps = *rps; rps 1235 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps) rps 1237 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *new_ps = kv_get_ps(rps); rps 1240 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->requested_rps = *rps; rps 2653 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps, rps 2657 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2659 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 2660 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 2661 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 2664 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 2665 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 2667 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->vclk = 0; rps 2668 drivers/gpu/drm/amd/amdgpu/kv_dpm.c rps->dclk = 0; rps 2671 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 2672 drivers/gpu/drm/amd/amdgpu/kv_dpm.c adev->pm.dpm.boot_ps = rps; rps 2675 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 2676 drivers/gpu/drm/amd/amdgpu/kv_dpm.c adev->pm.dpm.uvd_ps = rps; rps 2680 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps, int index, rps 2684 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2895 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; rps 2896 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2899 drivers/gpu/drm/amd/amdgpu/kv_dpm.c amdgpu_dpm_print_class_info(rps->class, rps->class2); rps 2900 drivers/gpu/drm/amd/amdgpu/kv_dpm.c amdgpu_dpm_print_cap_info(rps->caps); rps 2901 drivers/gpu/drm/amd/amdgpu/kv_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2908 drivers/gpu/drm/amd/amdgpu/kv_dpm.c amdgpu_dpm_print_ps_status(adev, rps); rps 3246 drivers/gpu/drm/amd/amdgpu/kv_dpm.c struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; rps 3249 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) rps 3253 drivers/gpu/drm/amd/amdgpu/kv_dpm.c kv_rps = kv_get_ps(rps); rps 3274 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); rps 3275 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); rps 1836 drivers/gpu/drm/amd/amdgpu/si_dpm.c static struct si_ps *si_get_ps(struct amdgpu_ps *rps); rps 3147 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps) rps 3149 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *new_ps = si_get_ps(rps); rps 3153 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->current_rps = *rps; rps 3160 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps) rps 3162 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *new_ps = si_get_ps(rps); rps 3166 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->requested_rps = *rps; rps 3428 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps) rps 3430 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 3466 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->vce_active) { rps 3467 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; rps 3468 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; rps 3469 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, rps 3472 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->evclk = 0; rps 3473 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->ecclk = 0; rps 3480 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->vclk || rps->dclk) { rps 3556 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->vce_active) { rps 3864 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = adev->pm.dpm.current_ps; rps 3865 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 7107 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps, rps 7111 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 7112 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 7113 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 7116 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 7117 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 7118 drivers/gpu/drm/amd/amdgpu/si_dpm.c } else if (r600_is_uvd_state(rps->class, rps->class2)) { rps 7119 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; rps 7120 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->dclk = RV770_DEFAULT_DCLK_FREQ; rps 7122 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->vclk = 0; rps 7123 drivers/gpu/drm/amd/amdgpu/si_dpm.c rps->dclk = 0; rps 7126 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 7127 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.boot_ps = rps; rps 7128 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 7129 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.uvd_ps = rps; rps 7133 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps, int index, rps 7139 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 7165 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { rps 7171 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && rps 7189 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 7199 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == rps 7487 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = &eg_pi->current_rps; rps 7488 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 7498 drivers/gpu/drm/amd/amdgpu/si_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 7898 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; rps 7899 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 7903 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_dpm_print_class_info(rps->class, rps->class2); rps 7904 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_dpm_print_cap_info(rps->caps); rps 7905 drivers/gpu/drm/amd/amdgpu/si_dpm.c DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 7915 drivers/gpu/drm/amd/amdgpu/si_dpm.c amdgpu_dpm_print_ps_status(adev, rps); rps 7948 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; rps 7951 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) rps 7955 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_rps = si_get_ps((struct amdgpu_ps *)rps); rps 7977 drivers/gpu/drm/amd/amdgpu/si_dpm.c *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); rps 7978 drivers/gpu/drm/amd/amdgpu/si_dpm.c *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); rps 7988 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = &eg_pi->current_rps; rps 7989 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *ps = si_get_ps(rps); rps 239 drivers/gpu/drm/amd/include/kgd_pp_interface.h void *rps, rps 1007 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_rps *rps = >->i915->gt_pm.rps; rps 1047 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; rps 1048 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; rps 1053 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_rps *rps = >->i915->gt_pm.rps; rps 1073 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; rps 1074 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; rps 775 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 814 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq)); rps 817 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); rps 820 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq)); rps 823 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq)); rps 827 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq)); rps 915 drivers/gpu/drm/i915/i915_debugfs.c rps->pm_intrmsk_mbz); rps 936 drivers/gpu/drm/i915/i915_debugfs.c rps->power.up_threshold); rps 945 drivers/gpu/drm/i915/i915_debugfs.c rps->power.down_threshold); rps 967 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); rps 970 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq)); rps 973 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq)); rps 975 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq)); rps 977 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->boost_freq)); rps 979 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); rps 982 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq)); rps 1442 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 1450 drivers/gpu/drm/i915/i915_debugfs.c min_gpu_freq = rps->min_freq; rps 1451 drivers/gpu/drm/i915/i915_debugfs.c max_gpu_freq = rps->max_freq; rps 1714 drivers/gpu/drm/i915/i915_debugfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 1715 drivers/gpu/drm/i915/i915_debugfs.c u32 act_freq = rps->cur_freq; rps 1731 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "RPS enabled? %d\n", rps->enabled); rps 1734 drivers/gpu/drm/i915/i915_debugfs.c atomic_read(&rps->num_waiters)); rps 1735 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); rps 1737 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->cur_freq), rps 1740 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq), rps 1741 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->min_freq_softlimit), rps 1742 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq_softlimit), rps 1743 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->max_freq)); rps 1745 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->idle_freq), rps 1746 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->efficient_freq), rps 1747 drivers/gpu/drm/i915/i915_debugfs.c intel_gpu_freq(dev_priv, rps->boost_freq)); rps 1749 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts)); rps 1751 drivers/gpu/drm/i915/i915_debugfs.c if (INTEL_GEN(dev_priv) >= 6 && rps->enabled && dev_priv->gt.awake) { rps 1763 drivers/gpu/drm/i915/i915_debugfs.c rps_power_to_str(rps->power.mode)); rps 1766 drivers/gpu/drm/i915/i915_debugfs.c rps->power.up_threshold); rps 1769 drivers/gpu/drm/i915/i915_debugfs.c rps->power.down_threshold); rps 607 drivers/gpu/drm/i915/i915_drv.h struct intel_rps rps; rps 346 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; rps 357 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; rps 364 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 366 drivers/gpu/drm/i915/i915_irq.c if (READ_ONCE(rps->interrupts_enabled)) rps 370 drivers/gpu/drm/i915/i915_irq.c WARN_ON_ONCE(rps->pm_iir); rps 377 drivers/gpu/drm/i915/i915_irq.c rps->interrupts_enabled = true; rps 385 drivers/gpu/drm/i915/i915_irq.c return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; rps 390 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 393 drivers/gpu/drm/i915/i915_irq.c if (!READ_ONCE(rps->interrupts_enabled)) rps 397 drivers/gpu/drm/i915/i915_irq.c rps->interrupts_enabled = false; rps 411 drivers/gpu/drm/i915/i915_irq.c cancel_work_sync(&rps->work); rps 1126 drivers/gpu/drm/i915/i915_irq.c memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei)); rps 1131 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 1132 drivers/gpu/drm/i915/i915_irq.c const struct intel_rps_ei *prev = &rps->ei; rps 1159 drivers/gpu/drm/i915/i915_irq.c if (c0 > time * rps->power.up_threshold) rps 1161 drivers/gpu/drm/i915/i915_irq.c else if (c0 < time * rps->power.down_threshold) rps 1165 drivers/gpu/drm/i915/i915_irq.c rps->ei = now; rps 1172 drivers/gpu/drm/i915/i915_irq.c container_of(work, struct drm_i915_private, gt_pm.rps.work); rps 1174 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 1180 drivers/gpu/drm/i915/i915_irq.c if (rps->interrupts_enabled) { rps 1181 drivers/gpu/drm/i915/i915_irq.c pm_iir = fetch_and_zero(&rps->pm_iir); rps 1182 drivers/gpu/drm/i915/i915_irq.c client_boost = atomic_read(&rps->num_waiters); rps 1191 drivers/gpu/drm/i915/i915_irq.c mutex_lock(&rps->lock); rps 1195 drivers/gpu/drm/i915/i915_irq.c adj = rps->last_adj; rps 1196 drivers/gpu/drm/i915/i915_irq.c new_delay = rps->cur_freq; rps 1197 drivers/gpu/drm/i915/i915_irq.c min = rps->min_freq_softlimit; rps 1198 drivers/gpu/drm/i915/i915_irq.c max = rps->max_freq_softlimit; rps 1200 drivers/gpu/drm/i915/i915_irq.c max = rps->max_freq; rps 1201 drivers/gpu/drm/i915/i915_irq.c if (client_boost && new_delay < rps->boost_freq) { rps 1202 drivers/gpu/drm/i915/i915_irq.c new_delay = rps->boost_freq; rps 1210 drivers/gpu/drm/i915/i915_irq.c if (new_delay >= rps->max_freq_softlimit) rps 1215 drivers/gpu/drm/i915/i915_irq.c if (rps->cur_freq > rps->efficient_freq) rps 1216 drivers/gpu/drm/i915/i915_irq.c new_delay = rps->efficient_freq; rps 1217 drivers/gpu/drm/i915/i915_irq.c else if (rps->cur_freq > rps->min_freq_softlimit) rps 1218 drivers/gpu/drm/i915/i915_irq.c new_delay = rps->min_freq_softlimit; rps 1226 drivers/gpu/drm/i915/i915_irq.c if (new_delay <= rps->min_freq_softlimit) rps 1232 drivers/gpu/drm/i915/i915_irq.c rps->last_adj = adj; rps 1242 drivers/gpu/drm/i915/i915_irq.c if ((adj < 0 && rps->power.mode == HIGH_POWER) || rps 1243 drivers/gpu/drm/i915/i915_irq.c (adj > 0 && rps->power.mode == LOW_POWER)) rps 1244 drivers/gpu/drm/i915/i915_irq.c rps->last_adj = 0; rps 1254 drivers/gpu/drm/i915/i915_irq.c rps->last_adj = 0; rps 1257 drivers/gpu/drm/i915/i915_irq.c mutex_unlock(&rps->lock); rps 1262 drivers/gpu/drm/i915/i915_irq.c if (rps->interrupts_enabled) rps 1661 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &i915->gt_pm.rps; rps 1671 drivers/gpu/drm/i915/i915_irq.c if (!rps->interrupts_enabled) rps 1674 drivers/gpu/drm/i915/i915_irq.c rps->pm_iir |= events; rps 1675 drivers/gpu/drm/i915/i915_irq.c schedule_work(&rps->work); rps 1680 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 1686 drivers/gpu/drm/i915/i915_irq.c if (rps->interrupts_enabled) { rps 1687 drivers/gpu/drm/i915/i915_irq.c rps->pm_iir |= pm_iir & dev_priv->pm_rps_events; rps 1688 drivers/gpu/drm/i915/i915_irq.c schedule_work(&rps->work); rps 4320 drivers/gpu/drm/i915/i915_irq.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 4328 drivers/gpu/drm/i915/i915_irq.c INIT_WORK(&rps->work, gen6_pm_rps_work); rps 4351 drivers/gpu/drm/i915/i915_irq.c rps->pm_intrmsk_mbz = 0; rps 4360 drivers/gpu/drm/i915/i915_irq.c rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; rps 4363 drivers/gpu/drm/i915/i915_irq.c rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; rps 234 drivers/gpu/drm/i915/i915_pmu.c val = i915->gt_pm.rps.cur_freq; rps 248 drivers/gpu/drm/i915/i915_pmu.c intel_gpu_freq(i915, i915->gt_pm.rps.cur_freq), rps 292 drivers/gpu/drm/i915/i915_request.c GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); rps 293 drivers/gpu/drm/i915/i915_request.c atomic_dec(&rq->i915->gt_pm.rps.num_waiters); rps 291 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.cur_freq)); rps 300 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.boost_freq)); rps 308 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 319 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || val > rps->max_freq) rps 322 drivers/gpu/drm/i915/i915_sysfs.c mutex_lock(&rps->lock); rps 323 drivers/gpu/drm/i915/i915_sysfs.c if (val != rps->boost_freq) { rps 324 drivers/gpu/drm/i915/i915_sysfs.c rps->boost_freq = val; rps 325 drivers/gpu/drm/i915/i915_sysfs.c boost = atomic_read(&rps->num_waiters); rps 327 drivers/gpu/drm/i915/i915_sysfs.c mutex_unlock(&rps->lock); rps 329 drivers/gpu/drm/i915/i915_sysfs.c schedule_work(&rps->work); rps 341 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.efficient_freq)); rps 350 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.max_freq_softlimit)); rps 358 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 368 drivers/gpu/drm/i915/i915_sysfs.c mutex_lock(&rps->lock); rps 371 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || rps 372 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq || rps 373 drivers/gpu/drm/i915/i915_sysfs.c val < rps->min_freq_softlimit) { rps 378 drivers/gpu/drm/i915/i915_sysfs.c if (val > rps->rp0_freq) rps 382 drivers/gpu/drm/i915/i915_sysfs.c rps->max_freq_softlimit = val; rps 384 drivers/gpu/drm/i915/i915_sysfs.c val = clamp_t(int, rps->cur_freq, rps 385 drivers/gpu/drm/i915/i915_sysfs.c rps->min_freq_softlimit, rps 386 drivers/gpu/drm/i915/i915_sysfs.c rps->max_freq_softlimit); rps 394 drivers/gpu/drm/i915/i915_sysfs.c mutex_unlock(&rps->lock); rps 406 drivers/gpu/drm/i915/i915_sysfs.c dev_priv->gt_pm.rps.min_freq_softlimit)); rps 414 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 424 drivers/gpu/drm/i915/i915_sysfs.c mutex_lock(&rps->lock); rps 427 drivers/gpu/drm/i915/i915_sysfs.c if (val < rps->min_freq || rps 428 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq || rps 429 drivers/gpu/drm/i915/i915_sysfs.c val > rps->max_freq_softlimit) { rps 434 drivers/gpu/drm/i915/i915_sysfs.c rps->min_freq_softlimit = val; rps 436 drivers/gpu/drm/i915/i915_sysfs.c val = clamp_t(int, rps->cur_freq, rps 437 drivers/gpu/drm/i915/i915_sysfs.c rps->min_freq_softlimit, rps 438 drivers/gpu/drm/i915/i915_sysfs.c rps->max_freq_softlimit); rps 446 drivers/gpu/drm/i915/i915_sysfs.c mutex_unlock(&rps->lock); rps 469 drivers/gpu/drm/i915/i915_sysfs.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 473 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp0_freq); rps 475 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->rp1_freq); rps 477 drivers/gpu/drm/i915/i915_sysfs.c val = intel_gpu_freq(dev_priv, rps->min_freq); rps 6544 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6554 drivers/gpu/drm/i915/intel_pm.c limits = (rps->max_freq_softlimit) << 23; rps 6555 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) rps 6556 drivers/gpu/drm/i915/intel_pm.c limits |= (rps->min_freq_softlimit) << 14; rps 6558 drivers/gpu/drm/i915/intel_pm.c limits = rps->max_freq_softlimit << 24; rps 6559 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) rps 6560 drivers/gpu/drm/i915/intel_pm.c limits |= rps->min_freq_softlimit << 16; rps 6568 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6572 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&rps->power.mutex); rps 6574 drivers/gpu/drm/i915/intel_pm.c if (new_power == rps->power.mode) rps 6637 drivers/gpu/drm/i915/intel_pm.c rps->power.mode = new_power; rps 6638 drivers/gpu/drm/i915/intel_pm.c rps->power.up_threshold = threshold_up; rps 6639 drivers/gpu/drm/i915/intel_pm.c rps->power.down_threshold = threshold_down; rps 6644 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6647 drivers/gpu/drm/i915/intel_pm.c new_power = rps->power.mode; rps 6648 drivers/gpu/drm/i915/intel_pm.c switch (rps->power.mode) { rps 6650 drivers/gpu/drm/i915/intel_pm.c if (val > rps->efficient_freq + 1 && rps 6651 drivers/gpu/drm/i915/intel_pm.c val > rps->cur_freq) rps 6656 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->efficient_freq && rps 6657 drivers/gpu/drm/i915/intel_pm.c val < rps->cur_freq) rps 6659 drivers/gpu/drm/i915/intel_pm.c else if (val >= rps->rp0_freq && rps 6660 drivers/gpu/drm/i915/intel_pm.c val > rps->cur_freq) rps 6665 drivers/gpu/drm/i915/intel_pm.c if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && rps 6666 drivers/gpu/drm/i915/intel_pm.c val < rps->cur_freq) rps 6671 drivers/gpu/drm/i915/intel_pm.c if (val <= rps->min_freq_softlimit) rps 6673 drivers/gpu/drm/i915/intel_pm.c if (val >= rps->max_freq_softlimit) rps 6676 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&rps->power.mutex); rps 6677 drivers/gpu/drm/i915/intel_pm.c if (rps->power.interactive) rps 6680 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&rps->power.mutex); rps 6685 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &i915->gt_pm.rps; rps 6690 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&rps->power.mutex); rps 6692 drivers/gpu/drm/i915/intel_pm.c if (!rps->power.interactive++ && READ_ONCE(i915->gt.awake)) rps 6695 drivers/gpu/drm/i915/intel_pm.c GEM_BUG_ON(!rps->power.interactive); rps 6696 drivers/gpu/drm/i915/intel_pm.c rps->power.interactive--; rps 6698 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&rps->power.mutex); rps 6703 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6707 drivers/gpu/drm/i915/intel_pm.c if (val > rps->min_freq_softlimit) rps 6709 drivers/gpu/drm/i915/intel_pm.c if (val < rps->max_freq_softlimit) rps 6722 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6727 drivers/gpu/drm/i915/intel_pm.c if (val != rps->cur_freq) { rps 6749 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = val; rps 6765 drivers/gpu/drm/i915/intel_pm.c if (val != dev_priv->gt_pm.rps.cur_freq) { rps 6775 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.cur_freq = val; rps 6790 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6791 drivers/gpu/drm/i915/intel_pm.c u32 val = rps->idle_freq; rps 6794 drivers/gpu/drm/i915/intel_pm.c if (rps->cur_freq <= val) rps 6819 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6821 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&rps->lock); rps 6822 drivers/gpu/drm/i915/intel_pm.c if (rps->enabled) { rps 6828 drivers/gpu/drm/i915/intel_pm.c gen6_rps_pm_mask(dev_priv, rps->cur_freq)); rps 6835 drivers/gpu/drm/i915/intel_pm.c freq = max(rps->cur_freq, rps 6836 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq); rps 6840 drivers/gpu/drm/i915/intel_pm.c rps->min_freq_softlimit, rps 6841 drivers/gpu/drm/i915/intel_pm.c rps->max_freq_softlimit))) rps 6844 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&rps->lock); rps 6849 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6858 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&rps->lock); rps 6859 drivers/gpu/drm/i915/intel_pm.c if (rps->enabled) { rps 6863 drivers/gpu/drm/i915/intel_pm.c gen6_set_rps(dev_priv, rps->idle_freq); rps 6864 drivers/gpu/drm/i915/intel_pm.c rps->last_adj = 0; rps 6868 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&rps->lock); rps 6873 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &rq->i915->gt_pm.rps; rps 6880 drivers/gpu/drm/i915/intel_pm.c if (!rps->enabled) rps 6891 drivers/gpu/drm/i915/intel_pm.c boost = !atomic_fetch_inc(&rps->num_waiters); rps 6898 drivers/gpu/drm/i915/intel_pm.c if (READ_ONCE(rps->cur_freq) < rps->boost_freq) rps 6899 drivers/gpu/drm/i915/intel_pm.c schedule_work(&rps->work); rps 6901 drivers/gpu/drm/i915/intel_pm.c atomic_inc(&rps->boosts); rps 6906 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 6909 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&rps->lock); rps 6910 drivers/gpu/drm/i915/intel_pm.c GEM_BUG_ON(val > rps->max_freq); rps 6911 drivers/gpu/drm/i915/intel_pm.c GEM_BUG_ON(val < rps->min_freq); rps 6913 drivers/gpu/drm/i915/intel_pm.c if (!rps->enabled) { rps 6914 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = val; rps 7064 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7071 drivers/gpu/drm/i915/intel_pm.c rps->rp0_freq = (rp_state_cap >> 16) & 0xff; rps 7072 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = (rp_state_cap >> 8) & 0xff; rps 7073 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = (rp_state_cap >> 0) & 0xff; rps 7076 drivers/gpu/drm/i915/intel_pm.c rps->rp0_freq = (rp_state_cap >> 0) & 0xff; rps 7077 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = (rp_state_cap >> 8) & 0xff; rps 7078 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = (rp_state_cap >> 16) & 0xff; rps 7081 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = rps->rp0_freq; rps 7083 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = rps->rp1_freq; rps 7091 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = rps 7094 drivers/gpu/drm/i915/intel_pm.c rps->min_freq, rps 7095 drivers/gpu/drm/i915/intel_pm.c rps->max_freq); rps 7102 drivers/gpu/drm/i915/intel_pm.c rps->rp0_freq *= GEN9_FREQ_SCALER; rps 7103 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq *= GEN9_FREQ_SCALER; rps 7104 drivers/gpu/drm/i915/intel_pm.c rps->min_freq *= GEN9_FREQ_SCALER; rps 7105 drivers/gpu/drm/i915/intel_pm.c rps->max_freq *= GEN9_FREQ_SCALER; rps 7106 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq *= GEN9_FREQ_SCALER; rps 7113 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7114 drivers/gpu/drm/i915/intel_pm.c u8 freq = rps->cur_freq; rps 7117 drivers/gpu/drm/i915/intel_pm.c rps->power.mode = -1; rps 7118 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = -1; rps 7132 drivers/gpu/drm/i915/intel_pm.c GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); rps 7347 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7353 drivers/gpu/drm/i915/intel_pm.c HSW_FREQUENCY(rps->rp1_freq)); rps 7355 drivers/gpu/drm/i915/intel_pm.c HSW_FREQUENCY(rps->rp1_freq)); rps 7361 drivers/gpu/drm/i915/intel_pm.c rps->max_freq_softlimit << 24 | rps 7362 drivers/gpu/drm/i915/intel_pm.c rps->min_freq_softlimit << 16); rps 7475 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7483 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&rps->lock); rps 7485 drivers/gpu/drm/i915/intel_pm.c if (rps->max_freq <= rps->min_freq) rps 7507 drivers/gpu/drm/i915/intel_pm.c min_gpu_freq = rps->min_freq; rps 7508 drivers/gpu/drm/i915/intel_pm.c max_gpu_freq = rps->max_freq; rps 7766 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.gpll_ref_freq = rps 7772 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.gpll_ref_freq); rps 7777 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7804 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = valleyview_rps_max_freq(dev_priv); rps 7805 drivers/gpu/drm/i915/intel_pm.c rps->rp0_freq = rps->max_freq; rps 7807 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->max_freq), rps 7808 drivers/gpu/drm/i915/intel_pm.c rps->max_freq); rps 7810 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv); rps 7812 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->efficient_freq), rps 7813 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq); rps 7815 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = valleyview_rps_guar_freq(dev_priv); rps 7817 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->rp1_freq), rps 7818 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq); rps 7820 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = valleyview_rps_min_freq(dev_priv); rps 7822 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->min_freq), rps 7823 drivers/gpu/drm/i915/intel_pm.c rps->min_freq); rps 7833 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 7857 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = cherryview_rps_max_freq(dev_priv); rps 7858 drivers/gpu/drm/i915/intel_pm.c rps->rp0_freq = rps->max_freq; rps 7860 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->max_freq), rps 7861 drivers/gpu/drm/i915/intel_pm.c rps->max_freq); rps 7863 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv); rps 7865 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->efficient_freq), rps 7866 drivers/gpu/drm/i915/intel_pm.c rps->efficient_freq); rps 7868 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq = cherryview_rps_guar_freq(dev_priv); rps 7870 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->rp1_freq), rps 7871 drivers/gpu/drm/i915/intel_pm.c rps->rp1_freq); rps 7873 drivers/gpu/drm/i915/intel_pm.c rps->min_freq = cherryview_rps_min_freq(dev_priv); rps 7875 drivers/gpu/drm/i915/intel_pm.c intel_gpu_freq(dev_priv, rps->min_freq), rps 7876 drivers/gpu/drm/i915/intel_pm.c rps->min_freq); rps 7883 drivers/gpu/drm/i915/intel_pm.c WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq | rps 7884 drivers/gpu/drm/i915/intel_pm.c rps->min_freq) & 1, rps 8267 drivers/gpu/drm/i915/intel_pm.c pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq)); rps 8651 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 8673 drivers/gpu/drm/i915/intel_pm.c rps->max_freq_softlimit = rps->max_freq; rps 8674 drivers/gpu/drm/i915/intel_pm.c rps->min_freq_softlimit = rps->min_freq; rps 8685 drivers/gpu/drm/i915/intel_pm.c (rps->max_freq & 0xff) * 50, rps 8687 drivers/gpu/drm/i915/intel_pm.c rps->max_freq = params & 0xff; rps 8692 drivers/gpu/drm/i915/intel_pm.c rps->boost_freq = rps->max_freq; rps 8693 drivers/gpu/drm/i915/intel_pm.c rps->idle_freq = rps->min_freq; rps 8694 drivers/gpu/drm/i915/intel_pm.c rps->cur_freq = rps->idle_freq; rps 8710 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ rps 8722 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&i915->gt_pm.rps.lock); rps 8734 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); rps 8753 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 8755 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&rps->lock); rps 8757 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&rps->lock); rps 8762 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); rps 8764 drivers/gpu/drm/i915/intel_pm.c if (!dev_priv->gt_pm.rps.enabled) rps 8778 drivers/gpu/drm/i915/intel_pm.c dev_priv->gt_pm.rps.enabled = false; rps 8783 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->gt_pm.rps.lock); rps 8790 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->gt_pm.rps.lock); rps 8795 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&i915->gt_pm.rps.lock); rps 8807 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&dev_priv->gt_pm.rps.lock); rps 8833 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 8835 drivers/gpu/drm/i915/intel_pm.c lockdep_assert_held(&rps->lock); rps 8837 drivers/gpu/drm/i915/intel_pm.c if (rps->enabled) rps 8855 drivers/gpu/drm/i915/intel_pm.c WARN_ON(rps->max_freq < rps->min_freq); rps 8856 drivers/gpu/drm/i915/intel_pm.c WARN_ON(rps->idle_freq > rps->max_freq); rps 8858 drivers/gpu/drm/i915/intel_pm.c WARN_ON(rps->efficient_freq < rps->min_freq); rps 8859 drivers/gpu/drm/i915/intel_pm.c WARN_ON(rps->efficient_freq > rps->max_freq); rps 8861 drivers/gpu/drm/i915/intel_pm.c rps->enabled = true; rps 8870 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->gt_pm.rps.lock); rps 8879 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->gt_pm.rps.lock); rps 9858 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 9864 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); rps 9869 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 9871 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; rps 9876 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 9882 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); rps 9887 drivers/gpu/drm/i915/intel_pm.c struct intel_rps *rps = &dev_priv->gt_pm.rps; rps 9890 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; rps 9921 drivers/gpu/drm/i915/intel_pm.c mutex_init(&dev_priv->gt_pm.rps.lock); rps 9922 drivers/gpu/drm/i915/intel_pm.c mutex_init(&dev_priv->gt_pm.rps.power.mutex); rps 9924 drivers/gpu/drm/i915/intel_pm.c atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0); rps 52 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); rps 2097 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps) rps 2099 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2260 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps) rps 2262 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *new_ps = rv770_get_ps(rps); rps 2265 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->current_rps = *rps; rps 2271 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps) rps 2273 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *new_ps = rv770_get_ps(rps); rps 2276 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->requested_rps = *rps; rps 2740 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 2741 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2756 drivers/gpu/drm/radeon/btc_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2765 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 2766 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2788 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 2789 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 203 drivers/gpu/drm/radeon/ci_dpm.c static struct ci_ps *ci_get_ps(struct radeon_ps *rps) rps 205 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *ps = rps->ps_priv; rps 796 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps) rps 798 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *ps = ci_get_ps(rps); rps 805 drivers/gpu/drm/radeon/ci_dpm.c if (rps->vce_active) { rps 806 drivers/gpu/drm/radeon/ci_dpm.c rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; rps 807 drivers/gpu/drm/radeon/ci_dpm.c rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; rps 809 drivers/gpu/drm/radeon/ci_dpm.c rps->evclk = 0; rps 810 drivers/gpu/drm/radeon/ci_dpm.c rps->ecclk = 0; rps 819 drivers/gpu/drm/radeon/ci_dpm.c if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) rps 848 drivers/gpu/drm/radeon/ci_dpm.c if (rps->vce_active) { rps 5109 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps) rps 5111 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *new_ps = ci_get_ps(rps); rps 5114 drivers/gpu/drm/radeon/ci_dpm.c pi->current_rps = *rps; rps 5120 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps) rps 5122 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *new_ps = ci_get_ps(rps); rps 5125 drivers/gpu/drm/radeon/ci_dpm.c pi->requested_rps = *rps; rps 5452 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps, rps 5456 drivers/gpu/drm/radeon/ci_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 5457 drivers/gpu/drm/radeon/ci_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 5458 drivers/gpu/drm/radeon/ci_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 5461 drivers/gpu/drm/radeon/ci_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 5462 drivers/gpu/drm/radeon/ci_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 5464 drivers/gpu/drm/radeon/ci_dpm.c rps->vclk = 0; rps 5465 drivers/gpu/drm/radeon/ci_dpm.c rps->dclk = 0; rps 5468 drivers/gpu/drm/radeon/ci_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 5469 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.boot_ps = rps; rps 5470 drivers/gpu/drm/radeon/ci_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 5471 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 5475 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps, int index, rps 5479 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *ps = ci_get_ps(rps); rps 5497 drivers/gpu/drm/radeon/ci_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { rps 5501 drivers/gpu/drm/radeon/ci_dpm.c if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { rps 5508 drivers/gpu/drm/radeon/ci_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 5515 drivers/gpu/drm/radeon/ci_dpm.c switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { rps 5946 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 5951 drivers/gpu/drm/radeon/ci_dpm.c seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); rps 5957 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ps *rps) rps 5959 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ps *ps = ci_get_ps(rps); rps 5963 drivers/gpu/drm/radeon/ci_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 5964 drivers/gpu/drm/radeon/ci_dpm.c r600_dpm_print_cap_info(rps->caps); rps 5965 drivers/gpu/drm/radeon/ci_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 5971 drivers/gpu/drm/radeon/ci_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 46 drivers/gpu/drm/radeon/cypress_dpm.c struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); rps 244 drivers/gpu/drm/radeon/kv_dpm.c static struct kv_ps *kv_get_ps(struct radeon_ps *rps) rps 246 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *ps = rps->ps_priv; rps 1141 drivers/gpu/drm/radeon/kv_dpm.c struct radeon_ps *rps) rps 1143 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *new_ps = kv_get_ps(rps); rps 1146 drivers/gpu/drm/radeon/kv_dpm.c pi->current_rps = *rps; rps 1152 drivers/gpu/drm/radeon/kv_dpm.c struct radeon_ps *rps) rps 1154 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *new_ps = kv_get_ps(rps); rps 1157 drivers/gpu/drm/radeon/kv_dpm.c pi->requested_rps = *rps; rps 2585 drivers/gpu/drm/radeon/kv_dpm.c struct radeon_ps *rps, rps 2589 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2591 drivers/gpu/drm/radeon/kv_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 2592 drivers/gpu/drm/radeon/kv_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 2593 drivers/gpu/drm/radeon/kv_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 2596 drivers/gpu/drm/radeon/kv_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 2597 drivers/gpu/drm/radeon/kv_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 2599 drivers/gpu/drm/radeon/kv_dpm.c rps->vclk = 0; rps 2600 drivers/gpu/drm/radeon/kv_dpm.c rps->dclk = 0; rps 2603 drivers/gpu/drm/radeon/kv_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 2604 drivers/gpu/drm/radeon/kv_dpm.c rdev->pm.dpm.boot_ps = rps; rps 2607 drivers/gpu/drm/radeon/kv_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 2608 drivers/gpu/drm/radeon/kv_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 2612 drivers/gpu/drm/radeon/kv_dpm.c struct radeon_ps *rps, int index, rps 2616 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2850 drivers/gpu/drm/radeon/kv_dpm.c struct radeon_ps *rps) rps 2853 drivers/gpu/drm/radeon/kv_dpm.c struct kv_ps *ps = kv_get_ps(rps); rps 2855 drivers/gpu/drm/radeon/kv_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 2856 drivers/gpu/drm/radeon/kv_dpm.c r600_dpm_print_cap_info(rps->caps); rps 2857 drivers/gpu/drm/radeon/kv_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2864 drivers/gpu/drm/radeon/kv_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 735 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ni_get_ps(struct radeon_ps *rps) rps 737 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = rps->ps_priv; rps 788 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps) rps 790 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 3562 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps) rps 3564 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *new_ps = ni_get_ps(rps); rps 3568 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->current_rps = *rps; rps 3574 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps) rps 3576 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *new_ps = ni_get_ps(rps); rps 3580 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->requested_rps = *rps; rps 3895 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps, rps 3899 drivers/gpu/drm/radeon/ni_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 3900 drivers/gpu/drm/radeon/ni_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 3901 drivers/gpu/drm/radeon/ni_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 3904 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 3905 drivers/gpu/drm/radeon/ni_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 3906 drivers/gpu/drm/radeon/ni_dpm.c } else if (r600_is_uvd_state(rps->class, rps->class2)) { rps 3907 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; rps 3908 drivers/gpu/drm/radeon/ni_dpm.c rps->dclk = RV770_DEFAULT_DCLK_FREQ; rps 3910 drivers/gpu/drm/radeon/ni_dpm.c rps->vclk = 0; rps 3911 drivers/gpu/drm/radeon/ni_dpm.c rps->dclk = 0; rps 3914 drivers/gpu/drm/radeon/ni_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 3915 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.boot_ps = rps; rps 3916 drivers/gpu/drm/radeon/ni_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 3917 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 3921 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps, int index, rps 3926 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 3946 drivers/gpu/drm/radeon/ni_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { rps 3955 drivers/gpu/drm/radeon/ni_dpm.c if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { rps 3967 drivers/gpu/drm/radeon/ni_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 3976 drivers/gpu/drm/radeon/ni_dpm.c if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == rps 4283 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps) rps 4285 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 4289 drivers/gpu/drm/radeon/ni_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 4290 drivers/gpu/drm/radeon/ni_dpm.c r600_dpm_print_cap_info(rps->caps); rps 4291 drivers/gpu/drm/radeon/ni_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 4301 drivers/gpu/drm/radeon/ni_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 4308 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 4309 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 4319 drivers/gpu/drm/radeon/ni_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 4328 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 4329 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 4346 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 4347 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 237 drivers/gpu/drm/radeon/ni_dpm.h struct radeon_ps *rps); rps 239 drivers/gpu/drm/radeon/ni_dpm.h struct radeon_ps *rps); rps 144 drivers/gpu/drm/radeon/r600_dpm.c struct radeon_ps *rps) rps 147 drivers/gpu/drm/radeon/r600_dpm.c if (rps == rdev->pm.dpm.current_ps) rps 149 drivers/gpu/drm/radeon/r600_dpm.c if (rps == rdev->pm.dpm.requested_ps) rps 151 drivers/gpu/drm/radeon/r600_dpm.c if (rps == rdev->pm.dpm.boot_ps) rps 136 drivers/gpu/drm/radeon/r600_dpm.h struct radeon_ps *rps); rps 36 drivers/gpu/drm/radeon/rs780_dpm.c static struct igp_ps *rs780_get_ps(struct radeon_ps *rps) rps 38 drivers/gpu/drm/radeon/rs780_dpm.c struct igp_ps *ps = rps->ps_priv; rps 720 drivers/gpu/drm/radeon/rs780_dpm.c struct radeon_ps *rps, rps 724 drivers/gpu/drm/radeon/rs780_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 725 drivers/gpu/drm/radeon/rs780_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 726 drivers/gpu/drm/radeon/rs780_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 729 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 730 drivers/gpu/drm/radeon/rs780_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 732 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = 0; rps 733 drivers/gpu/drm/radeon/rs780_dpm.c rps->dclk = 0; rps 736 drivers/gpu/drm/radeon/rs780_dpm.c if (r600_is_uvd_state(rps->class, rps->class2)) { rps 737 drivers/gpu/drm/radeon/rs780_dpm.c if ((rps->vclk == 0) || (rps->dclk == 0)) { rps 738 drivers/gpu/drm/radeon/rs780_dpm.c rps->vclk = RS780_DEFAULT_VCLK_FREQ; rps 739 drivers/gpu/drm/radeon/rs780_dpm.c rps->dclk = RS780_DEFAULT_DCLK_FREQ; rps 743 drivers/gpu/drm/radeon/rs780_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 744 drivers/gpu/drm/radeon/rs780_dpm.c rdev->pm.dpm.boot_ps = rps; rps 745 drivers/gpu/drm/radeon/rs780_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 746 drivers/gpu/drm/radeon/rs780_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 750 drivers/gpu/drm/radeon/rs780_dpm.c struct radeon_ps *rps, rps 753 drivers/gpu/drm/radeon/rs780_dpm.c struct igp_ps *ps = rs780_get_ps(rps); rps 783 drivers/gpu/drm/radeon/rs780_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 941 drivers/gpu/drm/radeon/rs780_dpm.c struct radeon_ps *rps) rps 943 drivers/gpu/drm/radeon/rs780_dpm.c struct igp_ps *ps = rs780_get_ps(rps); rps 945 drivers/gpu/drm/radeon/rs780_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 946 drivers/gpu/drm/radeon/rs780_dpm.c r600_dpm_print_cap_info(rps->caps); rps 947 drivers/gpu/drm/radeon/rs780_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 952 drivers/gpu/drm/radeon/rs780_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 986 drivers/gpu/drm/radeon/rs780_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 987 drivers/gpu/drm/radeon/rs780_dpm.c struct igp_ps *ps = rs780_get_ps(rps); rps 996 drivers/gpu/drm/radeon/rs780_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 1033 drivers/gpu/drm/radeon/rs780_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 1034 drivers/gpu/drm/radeon/rs780_dpm.c struct igp_ps *ps = rs780_get_ps(rps); rps 1072 drivers/gpu/drm/radeon/rs780_dpm.c rs780_enable_voltage_scaling(rdev, rps); rps 36 drivers/gpu/drm/radeon/rv6xx_dpm.c static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps) rps 38 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rps->ps_priv; rps 1795 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps, rps 1798 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 1799 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 1800 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 1802 drivers/gpu/drm/radeon/rv6xx_dpm.c if (r600_is_uvd_state(rps->class, rps->class2)) { rps 1803 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; rps 1804 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; rps 1806 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->vclk = 0; rps 1807 drivers/gpu/drm/radeon/rv6xx_dpm.c rps->dclk = 0; rps 1810 drivers/gpu/drm/radeon/rv6xx_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 1811 drivers/gpu/drm/radeon/rv6xx_dpm.c rdev->pm.dpm.boot_ps = rps; rps 1812 drivers/gpu/drm/radeon/rv6xx_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 1813 drivers/gpu/drm/radeon/rv6xx_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 1817 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps, int index, rps 1820 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rv6xx_get_ps(rps); rps 1863 drivers/gpu/drm/radeon/rv6xx_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 2008 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps) rps 2010 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rv6xx_get_ps(rps); rps 2013 drivers/gpu/drm/radeon/rv6xx_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 2014 drivers/gpu/drm/radeon/rv6xx_dpm.c r600_dpm_print_cap_info(rps->caps); rps 2015 drivers/gpu/drm/radeon/rv6xx_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2025 drivers/gpu/drm/radeon/rv6xx_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 2031 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2032 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rv6xx_get_ps(rps); rps 2047 drivers/gpu/drm/radeon/rv6xx_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2056 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2057 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rv6xx_get_ps(rps); rps 2079 drivers/gpu/drm/radeon/rv6xx_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2080 drivers/gpu/drm/radeon/rv6xx_dpm.c struct rv6xx_ps *ps = rv6xx_get_ps(rps); rps 36 drivers/gpu/drm/radeon/rv730_dpm.c struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); rps 47 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps) rps 49 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rps->ps_priv; rps 2144 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps, rps 2148 drivers/gpu/drm/radeon/rv770_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 2149 drivers/gpu/drm/radeon/rv770_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 2150 drivers/gpu/drm/radeon/rv770_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 2153 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 2154 drivers/gpu/drm/radeon/rv770_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 2156 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = 0; rps 2157 drivers/gpu/drm/radeon/rv770_dpm.c rps->dclk = 0; rps 2160 drivers/gpu/drm/radeon/rv770_dpm.c if (r600_is_uvd_state(rps->class, rps->class2)) { rps 2161 drivers/gpu/drm/radeon/rv770_dpm.c if ((rps->vclk == 0) || (rps->dclk == 0)) { rps 2162 drivers/gpu/drm/radeon/rv770_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; rps 2163 drivers/gpu/drm/radeon/rv770_dpm.c rps->dclk = RV770_DEFAULT_DCLK_FREQ; rps 2167 drivers/gpu/drm/radeon/rv770_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 2168 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.boot_ps = rps; rps 2169 drivers/gpu/drm/radeon/rv770_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 2170 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 2174 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps, int index, rps 2179 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2224 drivers/gpu/drm/radeon/rv770_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { rps 2234 drivers/gpu/drm/radeon/rv770_dpm.c if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { rps 2248 drivers/gpu/drm/radeon/rv770_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 2257 drivers/gpu/drm/radeon/rv770_dpm.c if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == rps 2433 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps) rps 2435 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2438 drivers/gpu/drm/radeon/rv770_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 2439 drivers/gpu/drm/radeon/rv770_dpm.c r600_dpm_print_cap_info(rps->caps); rps 2440 drivers/gpu/drm/radeon/rv770_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2462 drivers/gpu/drm/radeon/rv770_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 2468 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2469 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2484 drivers/gpu/drm/radeon/rv770_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2497 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2498 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 2519 drivers/gpu/drm/radeon/rv770_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 2520 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *ps = rv770_get_ps(rps); rps 1742 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ni_get_ps(struct radeon_ps *rps); rps 2969 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps) rps 2971 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 3007 drivers/gpu/drm/radeon/si_dpm.c if (rps->vce_active) { rps 3008 drivers/gpu/drm/radeon/si_dpm.c rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; rps 3009 drivers/gpu/drm/radeon/si_dpm.c rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; rps 3010 drivers/gpu/drm/radeon/si_dpm.c si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, rps 3013 drivers/gpu/drm/radeon/si_dpm.c rps->evclk = 0; rps 3014 drivers/gpu/drm/radeon/si_dpm.c rps->ecclk = 0; rps 3021 drivers/gpu/drm/radeon/si_dpm.c if (rps->vclk || rps->dclk) { rps 3097 drivers/gpu/drm/radeon/si_dpm.c if (rps->vce_active) { rps 3404 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = rdev->pm.dpm.current_ps; rps 3405 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 6707 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps, rps 6711 drivers/gpu/drm/radeon/si_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 6712 drivers/gpu/drm/radeon/si_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 6713 drivers/gpu/drm/radeon/si_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 6716 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 6717 drivers/gpu/drm/radeon/si_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 6718 drivers/gpu/drm/radeon/si_dpm.c } else if (r600_is_uvd_state(rps->class, rps->class2)) { rps 6719 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = RV770_DEFAULT_VCLK_FREQ; rps 6720 drivers/gpu/drm/radeon/si_dpm.c rps->dclk = RV770_DEFAULT_DCLK_FREQ; rps 6722 drivers/gpu/drm/radeon/si_dpm.c rps->vclk = 0; rps 6723 drivers/gpu/drm/radeon/si_dpm.c rps->dclk = 0; rps 6726 drivers/gpu/drm/radeon/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) rps 6727 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.boot_ps = rps; rps 6728 drivers/gpu/drm/radeon/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 6729 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 6733 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps, int index, rps 6739 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 6765 drivers/gpu/drm/radeon/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { rps 6771 drivers/gpu/drm/radeon/si_dpm.c if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && rps 6789 drivers/gpu/drm/radeon/si_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 6799 drivers/gpu/drm/radeon/si_dpm.c if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == rps 7096 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 7097 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 7107 drivers/gpu/drm/radeon/si_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 7116 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 7117 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 7134 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; rps 7135 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *ps = ni_get_ps(rps); rps 74 drivers/gpu/drm/radeon/sumo_dpm.c static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) rps 76 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = rps->ps_priv; rps 342 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 345 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 385 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 388 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 664 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 667 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 714 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps, rps 717 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 737 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 739 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 985 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 988 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 1181 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 1183 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 1186 drivers/gpu/drm/radeon/sumo_dpm.c pi->current_rps = *rps; rps 1192 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 1194 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *new_ps = sumo_get_ps(rps); rps 1197 drivers/gpu/drm/radeon/sumo_dpm.c pi->requested_rps = *rps; rps 1403 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps, rps 1407 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1409 drivers/gpu/drm/radeon/sumo_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 1410 drivers/gpu/drm/radeon/sumo_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 1411 drivers/gpu/drm/radeon/sumo_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 1414 drivers/gpu/drm/radeon/sumo_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 1415 drivers/gpu/drm/radeon/sumo_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 1417 drivers/gpu/drm/radeon/sumo_dpm.c rps->vclk = 0; rps 1418 drivers/gpu/drm/radeon/sumo_dpm.c rps->dclk = 0; rps 1421 drivers/gpu/drm/radeon/sumo_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 1422 drivers/gpu/drm/radeon/sumo_dpm.c rdev->pm.dpm.boot_ps = rps; rps 1425 drivers/gpu/drm/radeon/sumo_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 1426 drivers/gpu/drm/radeon/sumo_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 1430 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps, int index, rps 1434 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1795 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps) rps 1798 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1800 drivers/gpu/drm/radeon/sumo_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 1801 drivers/gpu/drm/radeon/sumo_dpm.c r600_dpm_print_cap_info(rps->caps); rps 1802 drivers/gpu/drm/radeon/sumo_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 1809 drivers/gpu/drm/radeon/sumo_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 1816 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 1817 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1825 drivers/gpu/drm/radeon/sumo_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 1833 drivers/gpu/drm/radeon/sumo_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 1843 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 1844 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1903 drivers/gpu/drm/radeon/sumo_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 1904 drivers/gpu/drm/radeon/sumo_dpm.c struct sumo_ps *ps = sumo_get_ps(rps); rps 1912 drivers/gpu/drm/radeon/sumo_dpm.c sumo_enable_boost(rdev, rps, false); rps 1924 drivers/gpu/drm/radeon/sumo_dpm.c sumo_enable_boost(rdev, rps, false); rps 1939 drivers/gpu/drm/radeon/sumo_dpm.c sumo_enable_boost(rdev, rps, true); rps 349 drivers/gpu/drm/radeon/trinity_dpm.c static struct trinity_ps *trinity_get_ps(struct radeon_ps *rps) rps 351 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = rps->ps_priv; rps 871 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 873 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 897 drivers/gpu/drm/radeon/trinity_dpm.c static bool trinity_uvd_clocks_zero(struct radeon_ps *rps) rps 899 drivers/gpu/drm/radeon/trinity_dpm.c if ((rps->vclk == 0) && (rps->dclk == 0)) rps 1069 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 1071 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *new_ps = trinity_get_ps(rps); rps 1074 drivers/gpu/drm/radeon/trinity_dpm.c pi->current_rps = *rps; rps 1080 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 1082 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *new_ps = trinity_get_ps(rps); rps 1085 drivers/gpu/drm/radeon/trinity_dpm.c pi->requested_rps = *rps; rps 1185 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 1188 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *new_ps = trinity_get_ps(rps); rps 1206 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 1207 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 1453 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 1459 drivers/gpu/drm/radeon/trinity_dpm.c if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && rps 1460 drivers/gpu/drm/radeon/trinity_dpm.c (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) rps 1472 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 1474 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 1479 drivers/gpu/drm/radeon/trinity_dpm.c if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { rps 1480 drivers/gpu/drm/radeon/trinity_dpm.c high_index = trinity_get_uvd_clock_index(rdev, rps); rps 1682 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps, rps 1686 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 1688 drivers/gpu/drm/radeon/trinity_dpm.c rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); rps 1689 drivers/gpu/drm/radeon/trinity_dpm.c rps->class = le16_to_cpu(non_clock_info->usClassification); rps 1690 drivers/gpu/drm/radeon/trinity_dpm.c rps->class2 = le16_to_cpu(non_clock_info->usClassification2); rps 1693 drivers/gpu/drm/radeon/trinity_dpm.c rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); rps 1694 drivers/gpu/drm/radeon/trinity_dpm.c rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); rps 1696 drivers/gpu/drm/radeon/trinity_dpm.c rps->vclk = 0; rps 1697 drivers/gpu/drm/radeon/trinity_dpm.c rps->dclk = 0; rps 1700 drivers/gpu/drm/radeon/trinity_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { rps 1701 drivers/gpu/drm/radeon/trinity_dpm.c rdev->pm.dpm.boot_ps = rps; rps 1704 drivers/gpu/drm/radeon/trinity_dpm.c if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) rps 1705 drivers/gpu/drm/radeon/trinity_dpm.c rdev->pm.dpm.uvd_ps = rps; rps 1709 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps, int index, rps 1713 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 2013 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps) rps 2016 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 2018 drivers/gpu/drm/radeon/trinity_dpm.c r600_dpm_print_class_info(rps->class, rps->class2); rps 2019 drivers/gpu/drm/radeon/trinity_dpm.c r600_dpm_print_cap_info(rps->caps); rps 2020 drivers/gpu/drm/radeon/trinity_dpm.c printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2027 drivers/gpu/drm/radeon/trinity_dpm.c r600_dpm_print_ps_status(rdev, rps); rps 2034 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 2035 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 2045 drivers/gpu/drm/radeon/trinity_dpm.c seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); rps 2055 drivers/gpu/drm/radeon/trinity_dpm.c struct radeon_ps *rps = &pi->current_rps; rps 2056 drivers/gpu/drm/radeon/trinity_dpm.c struct trinity_ps *ps = trinity_get_ps(rps); rps 136 drivers/md/raid1.c struct resync_pages *rps; rps 142 drivers/md/raid1.c rps = kmalloc_array(pi->raid_disks, sizeof(struct resync_pages), rps 144 drivers/md/raid1.c if (!rps) rps 167 drivers/md/raid1.c struct resync_pages *rp = &rps[j]; rps 175 drivers/md/raid1.c memcpy(rp, &rps[0], sizeof(*rp)); rps 189 drivers/md/raid1.c resync_free_pages(&rps[j]); rps 194 drivers/md/raid1.c kfree(rps); rps 2607 drivers/md/raid1.c struct resync_pages *rps; rps 2613 drivers/md/raid1.c rps = bio->bi_private; rps 2615 drivers/md/raid1.c bio->bi_private = rps; rps 123 drivers/md/raid10.c struct resync_pages *rps; rps 140 drivers/md/raid10.c rps = kmalloc_array(nalloc_rp, sizeof(struct resync_pages), gfp_flags); rps 141 drivers/md/raid10.c if (!rps) rps 167 drivers/md/raid10.c rp = &rps[j]; rps 169 drivers/md/raid10.c rp_repl = &rps[nalloc + j]; rps 178 drivers/md/raid10.c memcpy(rp, &rps[0], sizeof(*rp)); rps 194 drivers/md/raid10.c resync_free_pages(&rps[j]); rps 204 drivers/md/raid10.c kfree(rps); rps 166 drivers/scsi/aic94xx/aic94xx_dev.c if (rps_resp->rps.affil_valid) rps 168 drivers/scsi/aic94xx/aic94xx_dev.c if (rps_resp->rps.affil_supp) rps 275 drivers/scsi/libsas/sas_ata.c memcpy(dev->frame_rcvd, &dev->sata_dev.rps_resp.rps.fis, rps 7396 drivers/scsi/lpfc/lpfc_els.c RPS *rps; rps 7407 drivers/scsi/lpfc/lpfc_els.c rps = (RPS *) lp; rps 7410 drivers/scsi/lpfc/lpfc_els.c ((flag == 1) && (be32_to_cpu(rps->un.portNum) == 0)) || rps 7411 drivers/scsi/lpfc/lpfc_els.c ((flag == 2) && (memcmp(&rps->un.portName, &vport->fc_portname, rps 4693 drivers/scsi/mpt3sas/mpt3sas_base.c struct reply_post_struct *rps; rps 4736 drivers/scsi/mpt3sas/mpt3sas_base.c rps = &ioc->reply_post[i]; rps 4737 drivers/scsi/mpt3sas/mpt3sas_base.c if (rps->reply_post_free) { rps 4740 drivers/scsi/mpt3sas/mpt3sas_base.c rps->reply_post_free, rps 4741 drivers/scsi/mpt3sas/mpt3sas_base.c rps->reply_post_free_dma); rps 4744 drivers/scsi/mpt3sas/mpt3sas_base.c rps->reply_post_free)); rps 4745 drivers/scsi/mpt3sas/mpt3sas_base.c rps->reply_post_free = NULL; rps 1280 drivers/staging/comedi/drivers/s626.c u32 *rps; rps 1290 drivers/staging/comedi/drivers/s626.c rps = (u32 *)devpriv->rps_buf.logical_base; rps 1299 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; rps 1300 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; rps 1312 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); rps 1313 drivers/staging/comedi/drivers/s626.c *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; rps 1314 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); rps 1316 drivers/staging/comedi/drivers/s626.c *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ rps 1317 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; rps 1320 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; rps 1322 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; rps 1342 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); rps 1343 drivers/staging/comedi/drivers/s626.c *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; rps 1345 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); rps 1346 drivers/staging/comedi/drivers/s626.c *rps++ = local_ppl; rps 1348 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; rps 1350 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; rps 1352 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; rps 1354 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); rps 1356 drivers/staging/comedi/drivers/s626.c *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; rps 1357 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); rps 1359 drivers/staging/comedi/drivers/s626.c *rps++ = local_ppl; rps 1361 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; rps 1363 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; rps 1365 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; rps 1376 drivers/staging/comedi/drivers/s626.c (u32)((unsigned long)rps - rps 1381 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_JUMP; rps 1382 drivers/staging/comedi/drivers/s626.c *rps++ = jmp_adrs; rps 1387 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; rps 1388 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; rps 1392 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); rps 1393 drivers/staging/comedi/drivers/s626.c *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; rps 1394 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_NOP; rps 1397 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); rps 1398 drivers/staging/comedi/drivers/s626.c *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; rps 1405 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; rps 1408 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_STREG | rps 1410 drivers/staging/comedi/drivers/s626.c *rps++ = (u32)devpriv->ana_buf.physical_base + rps 1432 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_NOP; rps 1439 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); rps 1440 drivers/staging/comedi/drivers/s626.c *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; rps 1441 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_NOP; rps 1443 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ rps 1444 drivers/staging/comedi/drivers/s626.c *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; rps 1450 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ rps 1453 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); rps 1454 drivers/staging/comedi/drivers/s626.c *rps++ = (u32)devpriv->ana_buf.physical_base + rps 1463 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_IRQ; rps 1466 drivers/staging/comedi/drivers/s626.c *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ rps 1467 drivers/staging/comedi/drivers/s626.c *rps++ = (u32)devpriv->rps_buf.physical_base; rps 362 include/linux/kprobes.h int register_kretprobes(struct kretprobe **rps, int num); rps 363 include/linux/kprobes.h void unregister_kretprobes(struct kretprobe **rps, int num); rps 412 include/linux/kprobes.h static inline int register_kretprobes(struct kretprobe **rps, int num) rps 419 include/linux/kprobes.h static inline void unregister_kretprobes(struct kretprobe **rps, int num) rps 471 include/scsi/sas.h struct report_phy_sata_resp rps; rps 702 include/scsi/sas.h struct report_phy_sata_resp rps; rps 145 include/uapi/linux/fd.h unsigned char rps; /* rotations per second */ rps 1983 kernel/kprobes.c int register_kretprobes(struct kretprobe **rps, int num) rps 1990 kernel/kprobes.c ret = register_kretprobe(rps[i]); rps 1993 kernel/kprobes.c unregister_kretprobes(rps, i); rps 2007 kernel/kprobes.c void unregister_kretprobes(struct kretprobe **rps, int num) rps 2015 kernel/kprobes.c if (__unregister_kprobe_top(&rps[i]->kp) < 0) rps 2016 kernel/kprobes.c rps[i]->kp.addr = NULL; rps 2021 kernel/kprobes.c if (rps[i]->kp.addr) { rps 2022 kernel/kprobes.c __unregister_kprobe_bottom(&rps[i]->kp); rps 2023 kernel/kprobes.c cleanup_rp_inst(rps[i]); rps 2036 kernel/kprobes.c int register_kretprobes(struct kretprobe **rps, int num) rps 2047 kernel/kprobes.c void unregister_kretprobes(struct kretprobe **rps, int num) rps 242 kernel/test_kprobes.c struct kretprobe *rps[2] = {&rp, &rp2}; rps 247 kernel/test_kprobes.c ret = register_kretprobes(rps, 2); rps 266 kernel/test_kprobes.c unregister_kretprobes(rps, 2);