rm200_pic_slave   153 arch/mips/sni/rm200.c static __iomem u8 *rm200_pic_slave;
rm200_pic_slave   167 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   182 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   199 arch/mips/sni/rm200.c 	writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
rm200_pic_slave   200 arch/mips/sni/rm200.c 	value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);
rm200_pic_slave   201 arch/mips/sni/rm200.c 	writeb(0x0A, rm200_pic_slave + PIC_CMD);
rm200_pic_slave   239 arch/mips/sni/rm200.c 		readb(rm200_pic_slave + PIC_IMR);
rm200_pic_slave   240 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   241 arch/mips/sni/rm200.c 		writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
rm200_pic_slave   309 arch/mips/sni/rm200.c 		writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
rm200_pic_slave   310 arch/mips/sni/rm200.c 		irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;
rm200_pic_slave   338 arch/mips/sni/rm200.c 	writeb(0xff, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   344 arch/mips/sni/rm200.c 	writeb(0x11, rm200_pic_slave + PIC_CMD);
rm200_pic_slave   345 arch/mips/sni/rm200.c 	writeb(8, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   346 arch/mips/sni/rm200.c 	writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   347 arch/mips/sni/rm200.c 	writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   351 arch/mips/sni/rm200.c 	writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
rm200_pic_slave   405 arch/mips/sni/rm200.c 	rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
rm200_pic_slave   406 arch/mips/sni/rm200.c 	if (!rm200_pic_slave) {