rl_reg            195 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
rl_reg            202 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
rl_reg            207 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 		rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
rl_reg            209 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);