Rd                446 arch/arm64/include/asm/insn.h 				       enum aarch64_insn_register Rd,
Rd                451 arch/arm64/include/asm/insn.h 			  enum aarch64_insn_register Rd,
Rd               1605 arch/arm64/kernel/insn.c 				       enum aarch64_insn_register Rd,
Rd               1628 arch/arm64/kernel/insn.c 	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
Rd               1636 arch/arm64/kernel/insn.c 			  enum aarch64_insn_register Rd,
Rd               1660 arch/arm64/kernel/insn.c 	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
Rd                 97 arch/arm64/net/bpf_jit.h #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
Rd                 98 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
Rd                101 arch/arm64/net/bpf_jit.h #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
Rd                102 arch/arm64/net/bpf_jit.h #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
Rd                104 arch/arm64/net/bpf_jit.h #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
Rd                107 arch/arm64/net/bpf_jit.h #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
Rd                108 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
Rd                111 arch/arm64/net/bpf_jit.h #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
Rd                113 arch/arm64/net/bpf_jit.h #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
Rd                116 arch/arm64/net/bpf_jit.h #define A64_LSL(sf, Rd, Rn, shift) ({	\
Rd                118 arch/arm64/net/bpf_jit.h 	A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
Rd                121 arch/arm64/net/bpf_jit.h #define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
Rd                123 arch/arm64/net/bpf_jit.h #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
Rd                126 arch/arm64/net/bpf_jit.h #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
Rd                127 arch/arm64/net/bpf_jit.h #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
Rd                130 arch/arm64/net/bpf_jit.h #define A64_MOVEW(sf, Rd, imm16, shift, type) \
Rd                131 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_movewide(Rd, imm16, shift, \
Rd                136 arch/arm64/net/bpf_jit.h #define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)
Rd                137 arch/arm64/net/bpf_jit.h #define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)
Rd                138 arch/arm64/net/bpf_jit.h #define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)
Rd                141 arch/arm64/net/bpf_jit.h #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
Rd                142 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
Rd                145 arch/arm64/net/bpf_jit.h #define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
Rd                146 arch/arm64/net/bpf_jit.h #define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
Rd                147 arch/arm64/net/bpf_jit.h #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
Rd                149 arch/arm64/net/bpf_jit.h #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
Rd                154 arch/arm64/net/bpf_jit.h #define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
Rd                157 arch/arm64/net/bpf_jit.h #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
Rd                158 arch/arm64/net/bpf_jit.h #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
Rd                159 arch/arm64/net/bpf_jit.h #define A64_REV64(Rd, Rn)     A64_DATA1(1, Rd, Rn, REVERSE_64)
Rd                163 arch/arm64/net/bpf_jit.h #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
Rd                165 arch/arm64/net/bpf_jit.h #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
Rd                166 arch/arm64/net/bpf_jit.h #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
Rd                167 arch/arm64/net/bpf_jit.h #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
Rd                168 arch/arm64/net/bpf_jit.h #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
Rd                172 arch/arm64/net/bpf_jit.h #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
Rd                175 arch/arm64/net/bpf_jit.h #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
Rd                178 arch/arm64/net/bpf_jit.h #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
Rd                181 arch/arm64/net/bpf_jit.h #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
Rd                182 arch/arm64/net/bpf_jit.h 	aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
Rd                185 arch/arm64/net/bpf_jit.h #define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
Rd                186 arch/arm64/net/bpf_jit.h #define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
Rd                187 arch/arm64/net/bpf_jit.h #define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
Rd                188 arch/arm64/net/bpf_jit.h #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)