ring_ctrl_dw2    1743 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
ring_ctrl_dw2    1747 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
ring_ctrl_dw2    1750 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	ring_ctrl_dw2 |= MTK_RING_VLD;
ring_ctrl_dw2    1753 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
ring_ctrl_dw2    1757 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
ring_ctrl_dw2    1760 drivers/net/ethernet/mediatek/mtk_eth_soc.c 	ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
ring_ctrl_dw2    1765 drivers/net/ethernet/mediatek/mtk_eth_soc.c 		mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));