ring_base 183 drivers/crypto/qat/qat_common/adf_transport.c uint64_t ring_base; ring_base 209 drivers/crypto/qat/qat_common/adf_transport.c ring_base = BUILD_RING_BASE_ADDR(ring->dma_addr, ring->ring_size); ring_base 211 drivers/crypto/qat/qat_common/adf_transport.c ring->ring_number, ring_base); ring_base 839 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 ring_base; ring_base 851 drivers/gpu/drm/i915/gvt/cmd_parser.c ring_base = dev_priv->engine[s->ring_id]->mmio_base; ring_base 852 drivers/gpu/drm/i915/gvt/cmd_parser.c nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); ring_base 513 drivers/gpu/drm/i915/gvt/handlers.c u32 ring_base; ring_base 523 drivers/gpu/drm/i915/gvt/handlers.c ring_base = dev_priv->engine[ring_id]->mmio_base; ring_base 526 drivers/gpu/drm/i915/gvt/handlers.c reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { ring_base 1641 drivers/gpu/drm/i915/gvt/handlers.c u32 ring_base; ring_base 1651 drivers/gpu/drm/i915/gvt/handlers.c ring_base = dev_priv->engine[ring_id]->mmio_base; ring_base 1654 drivers/gpu/drm/i915/gvt/handlers.c offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || ring_base 1655 drivers/gpu/drm/i915/gvt/handlers.c offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { ring_base 215 drivers/gpu/drm/i915/gvt/scheduler.c u32 ring_base = dev_priv->engine[ring_id]->mmio_base; ring_base 218 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_INSTDONE(ring_base); ring_base 220 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_ACTHD(ring_base); ring_base 222 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_ACTHD_UDW(ring_base); ring_base 579 drivers/gpu/drm/i915/gvt/scheduler.c u32 ring_base; ring_base 581 drivers/gpu/drm/i915/gvt/scheduler.c ring_base = dev_priv->engine[workload->ring_id]->mmio_base; ring_base 582 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_START(ring_base)) = workload->rb_start; ring_base 810 drivers/gpu/drm/i915/gvt/scheduler.c u32 ring_base; ring_base 830 drivers/gpu/drm/i915/gvt/scheduler.c ring_base = dev_priv->engine[workload->ring_id]->mmio_base; ring_base 831 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; ring_base 832 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; ring_base 616 drivers/net/ethernet/broadcom/bgmac.c static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, ring_base 621 drivers/net/ethernet/broadcom/bgmac.c BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); ring_base 622 drivers/net/ethernet/broadcom/bgmac.c BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); ring_base 633 drivers/net/ethernet/broadcom/bgmac.c ring->mmio_base = ring_base[i]; ring_base 658 drivers/net/ethernet/broadcom/bgmac.c ring->mmio_base = ring_base[i]; ring_base 66 drivers/net/ethernet/cisco/enic/vnic_cq.c writeq(paddr, &cq->ctrl->ring_base); ring_base 28 drivers/net/ethernet/cisco/enic/vnic_cq.h u64 ring_base; /* 0x00 */ ring_base 123 drivers/net/ethernet/cisco/enic/vnic_rq.c writeq(paddr, &rq->ctrl->ring_base); ring_base 31 drivers/net/ethernet/cisco/enic/vnic_rq.h u64 ring_base; /* 0x00 */ ring_base 143 drivers/net/ethernet/cisco/enic/vnic_wq.c writeq(paddr, &wq->ctrl->ring_base); ring_base 30 drivers/net/ethernet/cisco/enic/vnic_wq.h u64 ring_base; /* 0x00 */ ring_base 1024 drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c fep->rx_bd_base = fep->ring_base; ring_base 132 drivers/net/ethernet/freescale/fs_enet/fs_enet.h void __iomem *ring_base; ring_base 150 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, ring_base 154 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c if (fep->ring_base == NULL) ring_base 165 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c if (fep->ring_base) ring_base 168 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c (void __force *)fep->ring_base, fep->ring_mem_addr); ring_base 532 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c fep->ring_base); ring_base 551 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c (uint) (((void *)recheck_bd - fep->ring_base) + ring_base 134 drivers/net/ethernet/freescale/fs_enet/mac-fec.c fep->ring_base = (void __force __iomem *)dma_alloc_coherent(fep->dev, ring_base 138 drivers/net/ethernet/freescale/fs_enet/mac-fec.c if (fep->ring_base == NULL) ring_base 149 drivers/net/ethernet/freescale/fs_enet/mac-fec.c if(fep->ring_base) ring_base 152 drivers/net/ethernet/freescale/fs_enet/mac-fec.c (void __force *)fep->ring_base, ring_base 142 drivers/net/ethernet/freescale/fs_enet/mac-scc.c fep->ring_base = (void __iomem __force*) ring_base 152 drivers/net/ethernet/freescale/fs_enet/mac-scc.c if (fep->ring_base) ring_base 281 drivers/net/ethernet/pensando/ionic/ionic_dev.c .q_init.ring_base = cpu_to_le64(q->base_pa), ring_base 520 drivers/net/ethernet/pensando/ionic/ionic_if.h __le64 ring_base; ring_base 570 drivers/net/ethernet/pensando/ionic/ionic_lif.c .ring_base = cpu_to_le64(q->base_pa), ring_base 579 drivers/net/ethernet/pensando/ionic/ionic_lif.c dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); ring_base 616 drivers/net/ethernet/pensando/ionic/ionic_lif.c .ring_base = cpu_to_le64(q->base_pa), ring_base 624 drivers/net/ethernet/pensando/ionic/ionic_lif.c dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); ring_base 1901 drivers/net/ethernet/pensando/ionic/ionic_lif.c .ring_base = cpu_to_le64(q->base_pa), ring_base 1907 drivers/net/ethernet/pensando/ionic/ionic_lif.c dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); ring_base 13 drivers/net/wireless/mediatek/mt76/dma.c u32 ring_base) ring_base 20 drivers/net/wireless/mediatek/mt76/dma.c q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; ring_base 153 drivers/net/wireless/mediatek/mt76/mt76.h u32 ring_base); ring_base 1721 drivers/scsi/be2iscsi/be_main.c pasync_sge = pasync_ctx->async_header.ring_base; ring_base 1727 drivers/scsi/be2iscsi/be_main.c pasync_sge = pasync_ctx->async_data.ring_base; ring_base 2775 drivers/scsi/be2iscsi/be_main.c pasync_ctx->async_header.ring_base = ring_base 2815 drivers/scsi/be2iscsi/be_main.c pasync_ctx->async_data.ring_base = ring_base 581 drivers/scsi/be2iscsi/be_main.h void *ring_base; ring_base 61 drivers/scsi/fnic/vnic_cq.c writeq(paddr, &cq->ctrl->ring_base); ring_base 36 drivers/scsi/fnic/vnic_cq.h u64 ring_base; /* 0x00 */ ring_base 119 drivers/scsi/fnic/vnic_rq.c writeq(paddr, &rq->ctrl->ring_base); ring_base 49 drivers/scsi/fnic/vnic_rq.h u64 ring_base; /* 0x00 */ ring_base 162 drivers/scsi/fnic/vnic_wq.c writeq(paddr, &wq->ctrl->ring_base); ring_base 184 drivers/scsi/fnic/vnic_wq.c writeq(paddr, &wq->ctrl->ring_base); ring_base 46 drivers/scsi/fnic/vnic_wq.h u64 ring_base; /* 0x00 */ ring_base 109 drivers/scsi/fnic/vnic_wq_copy.c writeq(paddr, &wq->ctrl->ring_base); ring_base 62 drivers/scsi/snic/vnic_cq.c writeq(paddr, &cq->ctrl->ring_base); ring_base 26 drivers/scsi/snic/vnic_cq.h u64 ring_base; /* 0x00 */ ring_base 163 drivers/scsi/snic/vnic_wq.c writeq(paddr, &wq->ctrl->ring_base); ring_base 27 drivers/scsi/snic/vnic_wq.h u64 ring_base; /* 0x00 */ ring_base 91 sound/mips/sgio2audio.c void *ring_base; ring_base 359 sound/mips/sgio2audio.c src_base = (unsigned long) chip->ring_base | (ch << CHANNEL_RING_SHIFT); ring_base 407 sound/mips/sgio2audio.c dst_base = (unsigned long)chip->ring_base | (ch << CHANNEL_RING_SHIFT); ring_base 795 sound/mips/sgio2audio.c chip->ring_base, chip->ring_base_dma); ring_base 832 sound/mips/sgio2audio.c chip->ring_base = dma_alloc_coherent(card->dev, ring_base 835 sound/mips/sgio2audio.c if (chip->ring_base == NULL) {