ri_mask            21 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 		.ri_mask = _ri_mask				\
ri_mask           469 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 			   flow->prs_ri.ri_mask);
ri_mask            94 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 				    unsigned int ri, unsigned int ri_mask)
ri_mask            96 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	priv->prs_shadow[index].ri_mask = ri_mask;
ri_mask           767 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		unsigned int ri_mask;
ri_mask           782 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK;
ri_mask           783 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 		if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE)
ri_mask           866 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			       unsigned int ri, unsigned int ri_mask)
ri_mask           894 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
ri_mask           920 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
ri_mask           923 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 				 ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
ri_mask           988 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 			       unsigned int ri, unsigned int ri_mask)
ri_mask          1009 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
ri_mask          2411 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask)
ri_mask          2428 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c 	ri_byte_mask = (u8 *)&ri_mask;
ri_mask           277 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h 	u32 ri_mask;
ri_mask           292 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h 	u32 ri_mask;
ri_mask           310 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask);