rfHSSIPara2       608 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rfHSSIPara2       609 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
rfHSSIPara2        68 drivers/staging/rtl8188eu/hal/phy.c 		tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2,
rfHSSIPara2        78 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
rfHSSIPara2       237 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0);
rfHSSIPara2       240 drivers/staging/rtl8188eu/hal/rf_cfg.c 	phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0);
rfHSSIPara2       114 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h 	u32 rfHSSIPara2;	/*  wire parameter control2 : */
rfHSSIPara2       113 drivers/staging/rtl8192e/rtl8192e/r8190P_def.h 	u32 rfHSSIPara2;
rfHSSIPara2        94 drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c 		rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
rfHSSIPara2        96 drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c 		rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
rfHSSIPara2       124 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
rfHSSIPara2       126 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
rfHSSIPara2       127 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
rfHSSIPara2       422 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rfHSSIPara2       423 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
rfHSSIPara2       424 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
rfHSSIPara2       425 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
rfHSSIPara2       152 drivers/staging/rtl8192u/r8190_rtl8256.c 		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);	/* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
rfHSSIPara2       153 drivers/staging/rtl8192u/r8190_rtl8256.c 		rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	/* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
rfHSSIPara2       625 drivers/staging/rtl8192u/r8192U.h 	u32 rfHSSIPara2;
rfHSSIPara2       166 drivers/staging/rtl8192u/r819xU_phy.c 	rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
rfHSSIPara2       169 drivers/staging/rtl8192u/r819xU_phy.c 	rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
rfHSSIPara2       170 drivers/staging/rtl8192u/r819xU_phy.c 	rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
rfHSSIPara2       622 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rfHSSIPara2       623 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
rfHSSIPara2       624 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
rfHSSIPara2       625 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
rfHSSIPara2       416 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
rfHSSIPara2       417 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
rfHSSIPara2       130 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c 		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);	/*  Set 1 to 4 bits for 8255 */
rfHSSIPara2       133 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c 		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	/*  Set 0 to 12  bits for 8255 */
rfHSSIPara2        61 drivers/staging/rtl8723bs/include/hal_com_phycfg.h 	u32 rfHSSIPara2;		/*  wire parameter control2 : */