rf3wireOffset     596 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
rf3wireOffset     597 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
rf3wireOffset     106 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
rf3wireOffset     104 drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h 	u32 rf3wireOffset;	/*  LSSI data: */
rf3wireOffset     109 drivers/staging/rtl8192e/rtl8192e/r8190P_def.h 	u32 rf3wireOffset;
rf3wireOffset     105 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 			rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     112 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 			rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     137 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 		rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
rf3wireOffset     162 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 			rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     169 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 			rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     183 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
rf3wireOffset     191 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 			rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     402 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
rf3wireOffset     403 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
rf3wireOffset     404 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
rf3wireOffset     405 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
rf3wireOffset     613 drivers/staging/rtl8192u/r8192U.h 	u32 rf3wireOffset;
rf3wireOffset     143 drivers/staging/rtl8192u/r819xU_phy.c 			rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     152 drivers/staging/rtl8192u/r819xU_phy.c 			rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     184 drivers/staging/rtl8192u/r819xU_phy.c 		rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
rf3wireOffset     225 drivers/staging/rtl8192u/r819xU_phy.c 			rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     232 drivers/staging/rtl8192u/r819xU_phy.c 			rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     249 drivers/staging/rtl8192u/r819xU_phy.c 	rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
rf3wireOffset     259 drivers/staging/rtl8192u/r819xU_phy.c 			rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
rf3wireOffset     595 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
rf3wireOffset     596 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
rf3wireOffset     597 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
rf3wireOffset     598 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
rf3wireOffset     257 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
rf3wireOffset     413 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
rf3wireOffset     414 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
rf3wireOffset      58 drivers/staging/rtl8723bs/include/hal_com_phycfg.h 	u32 rf3wireOffset;		/*  LSSI data: */