reset_mask 33 drivers/clk/clk-twl6040.c const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */ reset_mask 36 drivers/clk/clk-twl6040.c ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); reset_mask 40 drivers/clk/clk-twl6040.c ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask); reset_mask 84 drivers/clk/sunxi/clk-usb.c u32 reset_mask; reset_mask 141 drivers/clk/sunxi/clk-usb.c if (data->reset_mask == 0) reset_mask 159 drivers/clk/sunxi/clk-usb.c reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; reset_mask 167 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), reset_mask 180 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(1) | BIT(0), reset_mask 191 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), reset_mask 202 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(2) | BIT(1) | BIT(0), reset_mask 214 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), reset_mask 225 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(19) | BIT(18) | BIT(17), reset_mask 239 drivers/clk/sunxi/clk-usb.c .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17), reset_mask 62 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) reset_mask 69 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, reset_mask); reset_mask 70 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, reset_mask); reset_mask 20 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask); reset_mask 4858 drivers/gpu/drm/radeon/cik.c u32 reset_mask = 0; reset_mask 4869 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_GFX; reset_mask 4872 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_CP; reset_mask 4877 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_RLC; reset_mask 4882 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_DMA; reset_mask 4887 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_DMA1; reset_mask 4892 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_DMA; reset_mask 4895 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_DMA1; reset_mask 4901 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_IH; reset_mask 4904 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_SEM; reset_mask 4907 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_GRBM; reset_mask 4910 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_VMC; reset_mask 4914 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_MC; reset_mask 4917 drivers/gpu/drm/radeon/cik.c reset_mask |= RADEON_RESET_DISPLAY; reset_mask 4920 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_MC) { reset_mask 4921 drivers/gpu/drm/radeon/cik.c DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); reset_mask 4922 drivers/gpu/drm/radeon/cik.c reset_mask &= ~RADEON_RESET_MC; reset_mask 4925 drivers/gpu/drm/radeon/cik.c return reset_mask; reset_mask 4936 drivers/gpu/drm/radeon/cik.c static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) reset_mask 4942 drivers/gpu/drm/radeon/cik.c if (reset_mask == 0) reset_mask 4945 drivers/gpu/drm/radeon/cik.c dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); reset_mask 4966 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 4972 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_DMA1) { reset_mask 4984 drivers/gpu/drm/radeon/cik.c if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) reset_mask 4987 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_CP) { reset_mask 4993 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_DMA) reset_mask 4996 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_DMA1) reset_mask 4999 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_DISPLAY) reset_mask 5002 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_RLC) reset_mask 5005 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_SEM) reset_mask 5008 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_IH) reset_mask 5011 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_GRBM) reset_mask 5014 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_VMC) reset_mask 5018 drivers/gpu/drm/radeon/cik.c if (reset_mask & RADEON_RESET_MC) reset_mask 5225 drivers/gpu/drm/radeon/cik.c u32 reset_mask; reset_mask 5232 drivers/gpu/drm/radeon/cik.c reset_mask = cik_gpu_check_soft_reset(rdev); reset_mask 5234 drivers/gpu/drm/radeon/cik.c if (reset_mask) reset_mask 5238 drivers/gpu/drm/radeon/cik.c cik_gpu_soft_reset(rdev, reset_mask); reset_mask 5240 drivers/gpu/drm/radeon/cik.c reset_mask = cik_gpu_check_soft_reset(rdev); reset_mask 5243 drivers/gpu/drm/radeon/cik.c if (reset_mask && radeon_hard_reset) reset_mask 5246 drivers/gpu/drm/radeon/cik.c reset_mask = cik_gpu_check_soft_reset(rdev); reset_mask 5248 drivers/gpu/drm/radeon/cik.c if (!reset_mask) reset_mask 5265 drivers/gpu/drm/radeon/cik.c u32 reset_mask = cik_gpu_check_soft_reset(rdev); reset_mask 5267 drivers/gpu/drm/radeon/cik.c if (!(reset_mask & (RADEON_RESET_GFX | reset_mask 777 drivers/gpu/drm/radeon/cik_sdma.c u32 reset_mask = cik_gpu_check_soft_reset(rdev); reset_mask 785 drivers/gpu/drm/radeon/cik_sdma.c if (!(reset_mask & mask)) { reset_mask 3828 drivers/gpu/drm/radeon/evergreen.c u32 reset_mask = 0; reset_mask 3838 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_GFX; reset_mask 3842 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_CP; reset_mask 3845 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; reset_mask 3850 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_DMA; reset_mask 3855 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_DMA; reset_mask 3860 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_RLC; reset_mask 3863 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_IH; reset_mask 3866 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_SEM; reset_mask 3869 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_GRBM; reset_mask 3872 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_VMC; reset_mask 3876 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_MC; reset_mask 3879 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_DISPLAY; reset_mask 3884 drivers/gpu/drm/radeon/evergreen.c reset_mask |= RADEON_RESET_VMC; reset_mask 3887 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_MC) { reset_mask 3888 drivers/gpu/drm/radeon/evergreen.c DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); reset_mask 3889 drivers/gpu/drm/radeon/evergreen.c reset_mask &= ~RADEON_RESET_MC; reset_mask 3892 drivers/gpu/drm/radeon/evergreen.c return reset_mask; reset_mask 3895 drivers/gpu/drm/radeon/evergreen.c static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) reset_mask 3901 drivers/gpu/drm/radeon/evergreen.c if (reset_mask == 0) reset_mask 3904 drivers/gpu/drm/radeon/evergreen.c dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); reset_mask 3911 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 3925 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { reset_mask 3939 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_CP) { reset_mask 3946 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_DMA) reset_mask 3949 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_DISPLAY) reset_mask 3952 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_RLC) reset_mask 3955 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_SEM) reset_mask 3958 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_IH) reset_mask 3961 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_GRBM) reset_mask 3964 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_VMC) reset_mask 3968 drivers/gpu/drm/radeon/evergreen.c if (reset_mask & RADEON_RESET_MC) reset_mask 4053 drivers/gpu/drm/radeon/evergreen.c u32 reset_mask; reset_mask 4060 drivers/gpu/drm/radeon/evergreen.c reset_mask = evergreen_gpu_check_soft_reset(rdev); reset_mask 4062 drivers/gpu/drm/radeon/evergreen.c if (reset_mask) reset_mask 4066 drivers/gpu/drm/radeon/evergreen.c evergreen_gpu_soft_reset(rdev, reset_mask); reset_mask 4068 drivers/gpu/drm/radeon/evergreen.c reset_mask = evergreen_gpu_check_soft_reset(rdev); reset_mask 4071 drivers/gpu/drm/radeon/evergreen.c if (reset_mask && radeon_hard_reset) reset_mask 4074 drivers/gpu/drm/radeon/evergreen.c reset_mask = evergreen_gpu_check_soft_reset(rdev); reset_mask 4076 drivers/gpu/drm/radeon/evergreen.c if (!reset_mask) reset_mask 4093 drivers/gpu/drm/radeon/evergreen.c u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); reset_mask 4095 drivers/gpu/drm/radeon/evergreen.c if (!(reset_mask & (RADEON_RESET_GFX | reset_mask 173 drivers/gpu/drm/radeon/evergreen_dma.c u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); reset_mask 175 drivers/gpu/drm/radeon/evergreen_dma.c if (!(reset_mask & RADEON_RESET_DMA)) { reset_mask 1748 drivers/gpu/drm/radeon/ni.c u32 reset_mask = 0; reset_mask 1759 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_GFX; reset_mask 1763 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_CP; reset_mask 1766 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; reset_mask 1771 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_DMA; reset_mask 1776 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_DMA1; reset_mask 1781 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_DMA; reset_mask 1784 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_DMA1; reset_mask 1789 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_RLC; reset_mask 1792 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_IH; reset_mask 1795 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_SEM; reset_mask 1798 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_GRBM; reset_mask 1801 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_VMC; reset_mask 1805 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_MC; reset_mask 1808 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_DISPLAY; reset_mask 1813 drivers/gpu/drm/radeon/ni.c reset_mask |= RADEON_RESET_VMC; reset_mask 1816 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_MC) { reset_mask 1817 drivers/gpu/drm/radeon/ni.c DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); reset_mask 1818 drivers/gpu/drm/radeon/ni.c reset_mask &= ~RADEON_RESET_MC; reset_mask 1821 drivers/gpu/drm/radeon/ni.c return reset_mask; reset_mask 1824 drivers/gpu/drm/radeon/ni.c static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) reset_mask 1830 drivers/gpu/drm/radeon/ni.c if (reset_mask == 0) reset_mask 1833 drivers/gpu/drm/radeon/ni.c dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); reset_mask 1848 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 1855 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_DMA1) { reset_mask 1869 drivers/gpu/drm/radeon/ni.c if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { reset_mask 1884 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_CP) { reset_mask 1890 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_DMA) reset_mask 1893 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_DMA1) reset_mask 1896 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_DISPLAY) reset_mask 1899 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_RLC) reset_mask 1902 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_SEM) reset_mask 1905 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_IH) reset_mask 1908 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_GRBM) reset_mask 1911 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_VMC) reset_mask 1915 drivers/gpu/drm/radeon/ni.c if (reset_mask & RADEON_RESET_MC) reset_mask 1958 drivers/gpu/drm/radeon/ni.c u32 reset_mask; reset_mask 1965 drivers/gpu/drm/radeon/ni.c reset_mask = cayman_gpu_check_soft_reset(rdev); reset_mask 1967 drivers/gpu/drm/radeon/ni.c if (reset_mask) reset_mask 1970 drivers/gpu/drm/radeon/ni.c cayman_gpu_soft_reset(rdev, reset_mask); reset_mask 1972 drivers/gpu/drm/radeon/ni.c reset_mask = cayman_gpu_check_soft_reset(rdev); reset_mask 1974 drivers/gpu/drm/radeon/ni.c if (reset_mask) reset_mask 1993 drivers/gpu/drm/radeon/ni.c u32 reset_mask = cayman_gpu_check_soft_reset(rdev); reset_mask 1995 drivers/gpu/drm/radeon/ni.c if (!(reset_mask & (RADEON_RESET_GFX | reset_mask 289 drivers/gpu/drm/radeon/ni_dma.c u32 reset_mask = cayman_gpu_check_soft_reset(rdev); reset_mask 297 drivers/gpu/drm/radeon/ni_dma.c if (!(reset_mask & mask)) { reset_mask 1618 drivers/gpu/drm/radeon/r600.c u32 reset_mask = 0; reset_mask 1629 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_GFX; reset_mask 1636 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_GFX; reset_mask 1641 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_CP; reset_mask 1644 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; reset_mask 1649 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_DMA; reset_mask 1654 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_RLC; reset_mask 1657 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_IH; reset_mask 1660 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_SEM; reset_mask 1663 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_GRBM; reset_mask 1666 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_VMC; reset_mask 1671 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_MC; reset_mask 1674 drivers/gpu/drm/radeon/r600.c reset_mask |= RADEON_RESET_DISPLAY; reset_mask 1677 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_MC) { reset_mask 1678 drivers/gpu/drm/radeon/r600.c DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); reset_mask 1679 drivers/gpu/drm/radeon/r600.c reset_mask &= ~RADEON_RESET_MC; reset_mask 1682 drivers/gpu/drm/radeon/r600.c return reset_mask; reset_mask 1685 drivers/gpu/drm/radeon/r600.c static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) reset_mask 1691 drivers/gpu/drm/radeon/r600.c if (reset_mask == 0) reset_mask 1694 drivers/gpu/drm/radeon/r600.c dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); reset_mask 1707 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 1721 drivers/gpu/drm/radeon/r600.c if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { reset_mask 1750 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_CP) { reset_mask 1757 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 1764 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_RLC) reset_mask 1767 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_SEM) reset_mask 1770 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_IH) reset_mask 1773 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_GRBM) reset_mask 1777 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_MC) reset_mask 1781 drivers/gpu/drm/radeon/r600.c if (reset_mask & RADEON_RESET_VMC) reset_mask 1884 drivers/gpu/drm/radeon/r600.c u32 reset_mask; reset_mask 1891 drivers/gpu/drm/radeon/r600.c reset_mask = r600_gpu_check_soft_reset(rdev); reset_mask 1893 drivers/gpu/drm/radeon/r600.c if (reset_mask) reset_mask 1897 drivers/gpu/drm/radeon/r600.c r600_gpu_soft_reset(rdev, reset_mask); reset_mask 1899 drivers/gpu/drm/radeon/r600.c reset_mask = r600_gpu_check_soft_reset(rdev); reset_mask 1902 drivers/gpu/drm/radeon/r600.c if (reset_mask && radeon_hard_reset) reset_mask 1905 drivers/gpu/drm/radeon/r600.c reset_mask = r600_gpu_check_soft_reset(rdev); reset_mask 1907 drivers/gpu/drm/radeon/r600.c if (!reset_mask) reset_mask 1924 drivers/gpu/drm/radeon/r600.c u32 reset_mask = r600_gpu_check_soft_reset(rdev); reset_mask 1926 drivers/gpu/drm/radeon/r600.c if (!(reset_mask & (RADEON_RESET_GFX | reset_mask 210 drivers/gpu/drm/radeon/r600_dma.c u32 reset_mask = r600_gpu_check_soft_reset(rdev); reset_mask 212 drivers/gpu/drm/radeon/r600_dma.c if (!(reset_mask & RADEON_RESET_DMA)) { reset_mask 3776 drivers/gpu/drm/radeon/si.c u32 reset_mask = 0; reset_mask 3787 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_GFX; reset_mask 3791 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_CP; reset_mask 3794 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; reset_mask 3799 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_RLC; reset_mask 3804 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_DMA; reset_mask 3809 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_DMA1; reset_mask 3814 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_DMA; reset_mask 3817 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_DMA1; reset_mask 3823 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_IH; reset_mask 3826 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_SEM; reset_mask 3829 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_GRBM; reset_mask 3832 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_VMC; reset_mask 3836 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_MC; reset_mask 3839 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_DISPLAY; reset_mask 3844 drivers/gpu/drm/radeon/si.c reset_mask |= RADEON_RESET_VMC; reset_mask 3847 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_MC) { reset_mask 3848 drivers/gpu/drm/radeon/si.c DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); reset_mask 3849 drivers/gpu/drm/radeon/si.c reset_mask &= ~RADEON_RESET_MC; reset_mask 3852 drivers/gpu/drm/radeon/si.c return reset_mask; reset_mask 3855 drivers/gpu/drm/radeon/si.c static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) reset_mask 3861 drivers/gpu/drm/radeon/si.c if (reset_mask == 0) reset_mask 3864 drivers/gpu/drm/radeon/si.c dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); reset_mask 3882 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_DMA) { reset_mask 3888 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_DMA1) { reset_mask 3902 drivers/gpu/drm/radeon/si.c if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) { reset_mask 3917 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_CP) { reset_mask 3923 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_DMA) reset_mask 3926 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_DMA1) reset_mask 3929 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_DISPLAY) reset_mask 3932 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_RLC) reset_mask 3935 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_SEM) reset_mask 3938 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_IH) reset_mask 3941 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_GRBM) reset_mask 3944 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_VMC) reset_mask 3947 drivers/gpu/drm/radeon/si.c if (reset_mask & RADEON_RESET_MC) reset_mask 4089 drivers/gpu/drm/radeon/si.c u32 reset_mask; reset_mask 4096 drivers/gpu/drm/radeon/si.c reset_mask = si_gpu_check_soft_reset(rdev); reset_mask 4098 drivers/gpu/drm/radeon/si.c if (reset_mask) reset_mask 4102 drivers/gpu/drm/radeon/si.c si_gpu_soft_reset(rdev, reset_mask); reset_mask 4104 drivers/gpu/drm/radeon/si.c reset_mask = si_gpu_check_soft_reset(rdev); reset_mask 4107 drivers/gpu/drm/radeon/si.c if (reset_mask && radeon_hard_reset) reset_mask 4110 drivers/gpu/drm/radeon/si.c reset_mask = si_gpu_check_soft_reset(rdev); reset_mask 4112 drivers/gpu/drm/radeon/si.c if (!reset_mask) reset_mask 4129 drivers/gpu/drm/radeon/si.c u32 reset_mask = si_gpu_check_soft_reset(rdev); reset_mask 4131 drivers/gpu/drm/radeon/si.c if (!(reset_mask & (RADEON_RESET_GFX | reset_mask 43 drivers/gpu/drm/radeon/si_dma.c u32 reset_mask = si_gpu_check_soft_reset(rdev); reset_mask 51 drivers/gpu/drm/radeon/si_dma.c if (!(reset_mask & mask)) { reset_mask 439 drivers/misc/cxl/hcalls.c u64 control_mask, u64 reset_mask) reset_mask 448 drivers/misc/cxl/hcalls.c control_mask, reset_mask); reset_mask 450 drivers/misc/cxl/hcalls.c unit_address, process_token, control_mask, reset_mask, reset_mask 453 drivers/misc/cxl/hcalls.c control_mask, reset_mask, retbuf[0], rc); reset_mask 168 drivers/misc/cxl/hcalls.h u64 control_mask, u64 reset_mask); reset_mask 610 drivers/misc/cxl/trace.h u64 control_mask, u64 reset_mask, unsigned long r4, reset_mask 614 drivers/misc/cxl/trace.h control_mask, reset_mask, r4, rc), reset_mask 620 drivers/misc/cxl/trace.h __field(u64, reset_mask) reset_mask 629 drivers/misc/cxl/trace.h __entry->reset_mask = reset_mask; reset_mask 639 drivers/misc/cxl/trace.h __entry->reset_mask, reset_mask 1941 drivers/net/ethernet/3com/3c59x.c int do_tx_reset = 0, reset_mask = 0; reset_mask 1969 drivers/net/ethernet/3com/3c59x.c reset_mask = 0x0108; /* Reset interface logic, but not download logic */ reset_mask 2033 drivers/net/ethernet/3com/3c59x.c issue_and_wait(dev, TxReset|reset_mask); reset_mask 73 drivers/net/ethernet/ibm/ibmveth.h unsigned long reset_mask, unsigned long set_mask, reset_mask 80 drivers/net/ethernet/ibm/ibmveth.h reset_mask, set_mask); reset_mask 1441 drivers/net/ethernet/smsc/smsc911x.c unsigned int reset_mask = HW_CFG_SRST_; reset_mask 1471 drivers/net/ethernet/smsc/smsc911x.c reset_mask = RESET_CTL_DIGITAL_RST_; reset_mask 1475 drivers/net/ethernet/smsc/smsc911x.c smsc911x_reg_write(pdata, reset_offset, reset_mask); reset_mask 1482 drivers/net/ethernet/smsc/smsc911x.c } while ((--timeout) && (temp & reset_mask)); reset_mask 1484 drivers/net/ethernet/smsc/smsc911x.c if (unlikely(temp & reset_mask)) { reset_mask 2260 drivers/net/wireless/ath/ath10k/htt.h int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, reset_mask 583 drivers/net/wireless/ath/ath10k/htt_tx.c int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, reset_mask 611 drivers/net/wireless/ath/ath10k/htt_tx.c memcpy(req->reset_types, &reset_mask, 3); reset_mask 366 drivers/net/wireless/ath/ath10k/hw.c .reset_mask = 0xffffffff, reset_mask 297 drivers/net/wireless/ath/ath10k/hw.h u32 reset_mask; reset_mask 33 drivers/reset/reset-ti-sci.c u32 reset_mask; reset_mask 91 drivers/reset/reset-ti-sci.c reset_state |= control->reset_mask; reset_mask 93 drivers/reset/reset-ti-sci.c reset_state &= ~control->reset_mask; reset_mask 169 drivers/reset/reset-ti-sci.c return reset_state & control->reset_mask; reset_mask 206 drivers/reset/reset-ti-sci.c control->reset_mask = reset_spec->args[1]; reset_mask 65 include/linux/ioc3.h int reset_mask; /* non-zero if you want the ioc3.c module to reset interrupts */