reserved_bits     470 arch/x86/include/asm/kvm_host.h 	u64 reserved_bits;
reserved_bits     250 arch/x86/kvm/pmu_amd.c 		if (!(data & pmu->reserved_bits)) {
reserved_bits     269 arch/x86/kvm/pmu_amd.c 	pmu->reserved_bits = 0xffffffff00200000ull;
reserved_bits     260 arch/x86/kvm/vmx/pmu_intel.c 			if (!(data & pmu->reserved_bits)) {
reserved_bits     283 arch/x86/kvm/vmx/pmu_intel.c 	pmu->reserved_bits = 0xffffffff00200000ull;
reserved_bits     327 arch/x86/kvm/vmx/pmu_intel.c 		pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
reserved_bits     347 arch/x86/kvm/x86.c 	u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
reserved_bits     350 arch/x86/kvm/x86.c 	if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
reserved_bits     915 arch/x86/kvm/x86.c 	u64 reserved_bits = CR4_RESERVED_BITS;
reserved_bits     918 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_OSXSAVE;
reserved_bits     921 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_SMEP;
reserved_bits     924 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_SMAP;
reserved_bits     927 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_FSGSBASE;
reserved_bits     930 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_PKE;
reserved_bits     934 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_LA57;
reserved_bits     937 arch/x86/kvm/x86.c 		reserved_bits |= X86_CR4_UMIP;
reserved_bits     939 arch/x86/kvm/x86.c 	return reserved_bits;
reserved_bits      30 drivers/gpu/drm/arm/display/include/malidp_product.h 			reserved_bits:6;