res_pool           37 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool;
res_pool           49 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool = &mc_bus->resource_pools[pool_type];
res_pool           50 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->type != pool_type)
res_pool           52 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->mc_bus != mc_bus)
res_pool           55 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_lock(&res_pool->mutex);
res_pool           57 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->max_count < 0)
res_pool           59 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count < 0 ||
res_pool           60 drivers/bus/fsl-mc/fsl-mc-allocator.c 	    res_pool->free_count > res_pool->max_count)
res_pool           75 drivers/bus/fsl-mc/fsl-mc-allocator.c 	resource->parent_pool = res_pool;
res_pool           77 drivers/bus/fsl-mc/fsl-mc-allocator.c 	list_add_tail(&resource->node, &res_pool->free_list);
res_pool           79 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count++;
res_pool           80 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->max_count++;
res_pool           83 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_unlock(&res_pool->mutex);
res_pool          102 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool;
res_pool          115 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool = resource->parent_pool;
res_pool          116 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool != &mc_bus->resource_pools[resource->type])
res_pool          119 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_lock(&res_pool->mutex);
res_pool          121 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->max_count <= 0)
res_pool          123 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count <= 0 ||
res_pool          124 drivers/bus/fsl-mc/fsl-mc-allocator.c 	    res_pool->free_count > res_pool->max_count)
res_pool          140 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count--;
res_pool          141 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->max_count--;
res_pool          147 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_unlock(&res_pool->mutex);
res_pool          179 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool;
res_pool          191 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool = &mc_bus->resource_pools[pool_type];
res_pool          192 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->mc_bus != mc_bus)
res_pool          195 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_lock(&res_pool->mutex);
res_pool          196 drivers/bus/fsl-mc/fsl-mc-allocator.c 	resource = list_first_entry_or_null(&res_pool->free_list,
res_pool          209 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (resource->parent_pool != res_pool)
res_pool          211 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count <= 0 ||
res_pool          212 drivers/bus/fsl-mc/fsl-mc-allocator.c 	    res_pool->free_count > res_pool->max_count)
res_pool          217 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count--;
res_pool          220 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_unlock(&res_pool->mutex);
res_pool          229 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool;
res_pool          231 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool = resource->parent_pool;
res_pool          232 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (resource->type != res_pool->type)
res_pool          235 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_lock(&res_pool->mutex);
res_pool          236 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count < 0 ||
res_pool          237 drivers/bus/fsl-mc/fsl-mc-allocator.c 	    res_pool->free_count >= res_pool->max_count)
res_pool          243 drivers/bus/fsl-mc/fsl-mc-allocator.c 	list_add_tail(&resource->node, &res_pool->free_list);
res_pool          244 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count++;
res_pool          246 drivers/bus/fsl-mc/fsl-mc-allocator.c 	mutex_unlock(&res_pool->mutex);
res_pool          356 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool =
res_pool          382 drivers/bus/fsl-mc/fsl-mc-allocator.c 		mc_dev_irq->resource.type = res_pool->type;
res_pool          384 drivers/bus/fsl-mc/fsl-mc-allocator.c 		mc_dev_irq->resource.parent_pool = res_pool;
res_pool          386 drivers/bus/fsl-mc/fsl-mc-allocator.c 		list_add_tail(&mc_dev_irq->resource.node, &res_pool->free_list);
res_pool          395 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->max_count = irq_count;
res_pool          396 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count = irq_count;
res_pool          413 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool =
res_pool          419 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->max_count == 0)
res_pool          422 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count != res_pool->max_count)
res_pool          425 drivers/bus/fsl-mc/fsl-mc-allocator.c 	INIT_LIST_HEAD(&res_pool->free_list);
res_pool          426 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->max_count = 0;
res_pool          427 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool->free_count = 0;
res_pool          444 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool;
res_pool          461 drivers/bus/fsl-mc/fsl-mc-allocator.c 	res_pool = &mc_bus->resource_pools[FSL_MC_POOL_IRQ];
res_pool          462 drivers/bus/fsl-mc/fsl-mc-allocator.c 	if (res_pool->free_count < irq_count) {
res_pool          539 drivers/bus/fsl-mc/fsl-mc-allocator.c 		struct fsl_mc_resource_pool *res_pool =
res_pool          542 drivers/bus/fsl-mc/fsl-mc-allocator.c 		res_pool->type = pool_type;
res_pool          543 drivers/bus/fsl-mc/fsl-mc-allocator.c 		res_pool->max_count = 0;
res_pool          544 drivers/bus/fsl-mc/fsl-mc-allocator.c 		res_pool->free_count = 0;
res_pool          545 drivers/bus/fsl-mc/fsl-mc-allocator.c 		res_pool->mc_bus = mc_bus;
res_pool          546 drivers/bus/fsl-mc/fsl-mc-allocator.c 		INIT_LIST_HEAD(&res_pool->free_list);
res_pool          547 drivers/bus/fsl-mc/fsl-mc-allocator.c 		mutex_init(&res_pool->mutex);
res_pool          557 drivers/bus/fsl-mc/fsl-mc-allocator.c 	struct fsl_mc_resource_pool *res_pool =
res_pool          561 drivers/bus/fsl-mc/fsl-mc-allocator.c 	list_for_each_entry_safe(resource, next, &res_pool->free_list, node) {
res_pool          593 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
res_pool          603 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			adev->dm.dc->res_pool->audios[i]->inst;
res_pool          931 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
res_pool          328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
res_pool          483 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
res_pool          730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	const struct resource_pool *pool = dc->res_pool;
res_pool          975 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
res_pool         1506 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (dc->res_pool->pp_smu)
res_pool         1507 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		pp = &dc->res_pool->pp_smu->rv_funcs;
res_pool          237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
res_pool           76 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          130 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool           92 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
res_pool          150 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
res_pool          151 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
res_pool          171 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
res_pool          172 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
res_pool          197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
res_pool          211 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	if (dc->res_pool->pp_smu)
res_pool          212 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
res_pool          281 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
res_pool          298 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
res_pool           67 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
res_pool           86 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          690 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
res_pool          691 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (!dc->res_pool)
res_pool          694 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
res_pool          699 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->funcs->update_bw_bounding_box)
res_pool          700 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
res_pool          754 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          797 drivers/gpu/drm/amd/display/dc/core/dc.c 	full_pipe_count = dc->res_pool->pipe_count;
res_pool          798 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
res_pool          802 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->res_pool->stream_enc_count);
res_pool          805 drivers/gpu/drm/amd/display/dc/core/dc.c 	dc->caps.max_audios = dc->res_pool->audio_count;
res_pool          811 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (dc->res_pool->dmcu != NULL)
res_pool          812 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
res_pool          846 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
res_pool          872 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
res_pool          991 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (enc_inst >= dc->res_pool->pipe_count)
res_pool          994 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (enc_inst >= dc->res_pool->stream_enc_count)
res_pool          997 drivers/gpu/drm/amd/display/dc/core/dc.c 	tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
res_pool          998 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->stream_enc[enc_inst]);
res_pool         1000 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (tg_inst >= dc->res_pool->timing_generator_count)
res_pool         1003 drivers/gpu/drm/amd/display/dc/core/dc.c 	tg = dc->res_pool->timing_generators[tg_inst];
res_pool         1014 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
res_pool         1015 drivers/gpu/drm/amd/display/dc/core/dc.c 			dc->res_pool->dp_clock_source,
res_pool         1093 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1095 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
res_pool         1218 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool         1884 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
res_pool         1902 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2041 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2061 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2110 drivers/gpu/drm/amd/display/dc/core/dc.c 				for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2129 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2155 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2203 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2219 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2249 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2281 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
res_pool         2293 drivers/gpu/drm/amd/display/dc/core/dc.c 	return dal_irq_service_set(dc->res_pool->irqs, src, enable);
res_pool         2298 drivers/gpu/drm/amd/display/dc/core/dc.c 	dal_irq_service_ack(dc->res_pool->irqs, src);
res_pool         2364 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct abm *abm = dc->res_pool->abm;
res_pool         2374 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct abm *abm = dc->res_pool->abm;
res_pool         2384 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
res_pool         2400 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->res_pool,
res_pool          316 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
res_pool          320 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
res_pool          332 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
res_pool          436 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		struct audio_support *aud_support = &link->dc->res_pool->audio_support;
res_pool          747 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct audio_support *aud_support = &link->dc->res_pool->audio_support;
res_pool         1242 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (link->dc->res_pool->funcs->link_init)
res_pool         1243 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		link->dc->res_pool->funcs->link_init(link);
res_pool         1320 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	link->link_enc = link->dc->res_pool->funcs->link_enc_create(
res_pool         2309 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = link->ctx->dc->res_pool->abm;
res_pool         2322 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = core_dc->res_pool->abm;
res_pool         2323 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool         2375 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = core_dc->res_pool->abm;
res_pool         2388 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool         1262 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
res_pool           73 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool           78 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 			link->dc->res_pool->dp_clock_source;
res_pool          178 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          130 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct resource_pool *res_pool = NULL;
res_pool          134 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce80_create_resource_pool(
res_pool          138 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce81_create_resource_pool(
res_pool          142 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce83_create_resource_pool(
res_pool          146 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce100_create_resource_pool(
res_pool          150 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce110_create_resource_pool(
res_pool          156 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce112_create_resource_pool(
res_pool          161 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dce120_create_resource_pool(
res_pool          168 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn10_create_resource_pool(init_data, dc);
res_pool          175 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn20_create_resource_pool(init_data, dc);
res_pool          180 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res_pool = dcn21_create_resource_pool(init_data, dc);
res_pool          188 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (res_pool != NULL) {
res_pool          190 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			res_pool->ref_clocks.xtalin_clock_inKhz =
res_pool          198 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			res_pool->ref_clocks.dccg_ref_clock_inKhz =
res_pool          199 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool          200 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool          201 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool          206 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	return res_pool;
res_pool          212 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (dc->res_pool)
res_pool          213 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc->res_pool->funcs->destroy(&dc->res_pool);
res_pool         1237 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct resource_pool *pool = dc->res_pool;
res_pool         1316 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct resource_pool *pool = dc->res_pool;
res_pool         1692 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
res_pool         1701 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
res_pool         1732 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				dc->res_pool,
res_pool         1739 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc->res_pool,
res_pool         1744 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					  dc->res_pool,
res_pool         1747 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->remove_stream_from_ctx)
res_pool         1748 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
res_pool         1910 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct resource_pool *pool = dc->res_pool;
res_pool         1958 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
res_pool         2045 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->validate_global) {
res_pool         2046 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		result = dc->res_pool->funcs->validate_global(dc, new_ctx);
res_pool         2054 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
res_pool         2060 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			if (dc->res_pool->funcs->get_default_swizzle_mode &&
res_pool         2063 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
res_pool         2077 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						dc->res_pool,
res_pool         2080 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
res_pool         2083 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						dc->res_pool,
res_pool         2092 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
res_pool         2537 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct resource_pool *pool = dc->res_pool;
res_pool         2749 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
res_pool         2778 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (dc->res_pool->funcs->validate_plane)
res_pool         2779 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
res_pool          396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
res_pool          422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
res_pool          161 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
res_pool          173 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
res_pool          477 drivers/gpu/drm/amd/display/dc/dc.h 	struct resource_pool *res_pool;
res_pool          466 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
res_pool          254 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
res_pool          294 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
res_pool          650 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
res_pool          113 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
res_pool          125 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
res_pool          773 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          201 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
res_pool          960 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (core_dc->res_pool->pp_smu)
res_pool          961 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pp_smu = core_dc->res_pool->pp_smu;
res_pool         1004 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->res_pool->pp_smu)
res_pool         1005 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pp_smu = dc->res_pool->pp_smu;
res_pool         1437 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
res_pool         1438 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->stream_enc[i]->funcs->dp_blank(
res_pool         1439 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					dc->res_pool->stream_enc[i]);
res_pool         1462 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
res_pool         1463 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->timing_generators[i]->funcs->disable_crtc(
res_pool         1464 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->timing_generators[i]);
res_pool         1472 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
res_pool         1473 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->res_pool->dp_clock_source) == false)
res_pool         1476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->clk_src_count; i++) {
res_pool         1477 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
res_pool         1478 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->clock_sources[i]) == false)
res_pool         1502 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
res_pool         1503 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		tg = dc->res_pool->timing_generators[i];
res_pool         1508 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1651 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
res_pool         1797 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
res_pool         1810 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1826 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
res_pool         1920 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 						update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
res_pool         1937 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 										dc->res_pool,
res_pool         1973 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2000 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count) {
res_pool         2001 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2049 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2074 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2375 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2376 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		xfm = dc->res_pool->transforms[i];
res_pool         2403 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2404 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         2414 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->audio_count; i++) {
res_pool         2415 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct audio *audio = dc->res_pool->audios[i];
res_pool         2419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	abm = dc->res_pool->abm;
res_pool         2425 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dmcu = dc->res_pool->dmcu;
res_pool         2441 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
res_pool         2590 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2601 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2623 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2649 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
res_pool         2650 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				dc->res_pool->transforms[fe_idx]);
res_pool         2655 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		struct resource_pool *res_pool,
res_pool         2690 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
res_pool          878 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->res_pool->underlay_pipe_index))
res_pool          906 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->res_pool->pipe_count,
res_pool          828 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->res_pool->pipe_count,
res_pool          900 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 				dc->res_pool->dp_clock_source;
res_pool          903 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			&context->res_ctx, dc->res_pool,
res_pool          911 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		dc->res_pool,
res_pool          807 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool           75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
res_pool          105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
res_pool          129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *pool = dc->res_pool;
res_pool          245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *pool = dc->res_pool;
res_pool          620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
res_pool          640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
res_pool          649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!dc->res_pool->hubps[i]->power_gated)
res_pool          673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
res_pool          675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
res_pool          689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
res_pool          697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
res_pool          698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
res_pool          715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
res_pool          843 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
res_pool          863 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool          867 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
res_pool          884 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          920 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubbub1_soft_reset(dc->res_pool->hubbub, true);
res_pool          922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          943 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	hubbub1_soft_reset(dc->res_pool->hubbub, false);
res_pool          944 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
res_pool          970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
res_pool          981 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct mpc *mpc = dc->res_pool->mpc;
res_pool         1035 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
res_pool         1088 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1089 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         1114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->mpc->funcs->mpc_init_single_inst(
res_pool         1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->res_pool->mpc, i);
res_pool         1125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         1127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct hubp *hubp = dc->res_pool->hubps[i];
res_pool         1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dpp *dpp = dc->res_pool->dpps[i];
res_pool         1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
res_pool         1157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
res_pool         1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
res_pool         1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
res_pool         1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct abm *abm = dc->res_pool->abm;
res_pool         1179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dmcu *dmcu = dc->res_pool->dmcu;
res_pool         1182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct resource_pool *res_pool = dc->res_pool;
res_pool         1188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
res_pool         1189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
res_pool         1217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		res_pool->ref_clocks.xtalin_clock_inKhz =
res_pool         1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (res_pool->dccg && res_pool->hubbub) {
res_pool         1223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
res_pool         1225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
res_pool         1227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
res_pool         1228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						res_pool->ref_clocks.dccg_ref_clock_inKhz,
res_pool         1229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
res_pool         1232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				res_pool->ref_clocks.dccg_ref_clock_inKhz =
res_pool         1233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool         1234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool         1235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool         1258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
res_pool         1260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
res_pool         1273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < res_pool->audio_count; i++) {
res_pool         1274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct audio *audio = res_pool->audios[i];
res_pool         1312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
res_pool         2190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct mpc *mpc = dc->res_pool->mpc;
res_pool         2250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					dc->res_pool->mpc, mpcc_id);
res_pool         2253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
res_pool         2303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (dc->res_pool->dccg)
res_pool         2304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->dccg->funcs->update_dpp_dto(
res_pool         2305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					dc->res_pool->dccg,
res_pool         2533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool         2659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool         2666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
res_pool         2679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
res_pool         2689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
res_pool         2706 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
res_pool         2721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
res_pool         2738 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
res_pool         2871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
res_pool         2875 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < res_pool->pipe_count; i++) {
res_pool         2876 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (res_pool->hubps[i]->inst == mpcc_inst)
res_pool         2877 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			return res_pool->hubps[i];
res_pool         2885 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct resource_pool *res_pool,
res_pool         2899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
res_pool         2901 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
res_pool         2948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
res_pool         2961 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
res_pool         3112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool           80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
res_pool           84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
res_pool          112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
res_pool          190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool          506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	struct resource_pool *pool = dc->res_pool;
res_pool         1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
res_pool         1123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			dc->res_pool->hubbub,
res_pool         1432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		dc->res_pool = &pool->base;
res_pool          125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
res_pool          216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
res_pool          217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	opp = dc->res_pool->opps[opp_id_src0];
res_pool          221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
res_pool          222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		bottom_opp = dc->res_pool->opps[opp_id_src1];
res_pool          481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
res_pool          629 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = dc->res_pool->mpc;
res_pool          655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
res_pool         1166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool         1276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
res_pool         1286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
res_pool         1294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubbub *hubbub = dc->res_pool->hubbub;
res_pool         1299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
res_pool         1315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
res_pool         1322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
res_pool         1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
res_pool         1372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
res_pool         1392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
res_pool         1393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
res_pool         1506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
res_pool         1524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
res_pool         1652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
res_pool         1681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
res_pool         1685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (i == dc->res_pool->pipe_count)
res_pool         1700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
res_pool         1731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mpc *mpc = dc->res_pool->mpc;
res_pool         1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					dc->res_pool->mpc, mpcc_id);
res_pool         1790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
res_pool         1805 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_0 == 0)
res_pool         1807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_1 == 0)
res_pool         1809 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dc->res_pool->gsl_groups.gsl_2 == 0)
res_pool         1855 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_0 = 1;
res_pool         1859 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_1 = 1;
res_pool         1863 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_2 = 1;
res_pool         1881 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_0 = 0;
res_pool         1885 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_1 = 0;
res_pool         1889 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			dc->res_pool->gsl_groups.gsl_2 = 0;
res_pool         1997 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct resource_pool *res_pool = dc->res_pool;
res_pool         2004 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (res_pool->dccg->funcs->dccg_init)
res_pool         2005 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
res_pool         2024 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
res_pool         2025 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         2031 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < res_pool->timing_generator_count; i++) {
res_pool         2032 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         2038 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2039 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dpp *dpp = res_pool->dpps[i];
res_pool         2045 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
res_pool         2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
res_pool         2049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
res_pool         2050 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
res_pool         2052 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
res_pool         2055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         2058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct hubp *hubp = dc->res_pool->hubps[i];
res_pool         2059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dpp *dpp = dc->res_pool->dpps[i];
res_pool         2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
res_pool         2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
res_pool         2083 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
res_pool         2084 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
res_pool         2086 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
res_pool         2087 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         2093 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
res_pool         2103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
res_pool         1580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	const struct resource_pool *pool = dc->res_pool;
res_pool         1583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
res_pool         1840 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         1878 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
res_pool         1894 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
res_pool         2211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
res_pool         2349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
res_pool         2380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	int split_threshold = dc->res_pool->pipe_count / 2;
res_pool         2389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
res_pool         2420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (dc->res_pool->funcs->populate_dml_pipes)
res_pool         2443 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
res_pool         2486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
res_pool         2545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
res_pool         2548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&context->res_ctx, dc->res_pool,
res_pool         2585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
res_pool         2592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 							&context->res_ctx, dc->res_pool,
res_pool         2598 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						&context->res_ctx, dc->res_pool,
res_pool         2637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
res_pool         2676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (dc->res_pool->funcs->populate_dml_pipes)
res_pool         2677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
res_pool         2744 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
res_pool         2762 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2798 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
res_pool         2848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
res_pool         2965 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
res_pool         2966 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dc->res_pool->hubbub,
res_pool          993 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
res_pool          997 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
res_pool         1022 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (dc->res_pool->funcs->populate_dml_pipes)
res_pool         1023 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
res_pool         1072 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
res_pool         1276 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
res_pool          186 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	struct display_stream_compressor *dsc = dc->res_pool->dscs[0];
res_pool          267 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct resource_pool *res_pool,