res_cap           253 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct resource_caps *caps = pool->res_cap;
res_cap           394 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		if (line < pool->res_cap->num_ddc)
res_cap           361 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct resource_caps res_cap = {
res_cap           707 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           918 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	pool->base.res_cap = &res_cap;
res_cap           993 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
res_cap           994 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
res_cap          1045 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           764 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1282 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
res_cap          1289 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
res_cap          1291 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
res_cap          1403 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           726 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1153 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
res_cap          1160 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
res_cap          1161 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
res_cap          1292 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           450 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct resource_caps res_cap = {
res_cap           577 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           996 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.res_cap = &res_cap;
res_cap          1000 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
res_cap          1001 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
res_cap          1144 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           354 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct resource_caps res_cap = {
res_cap           755 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           884 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.res_cap = &res_cap;
res_cap           892 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
res_cap           893 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.timing_generator_count = res_cap.num_timing_generator;
res_cap          1008 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1081 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.res_cap = &res_cap_81;
res_cap          1205 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1278 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.res_cap = &res_cap_83;
res_cap          1398 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
res_cap          1258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
res_cap           494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct resource_caps res_cap = {
res_cap           931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.res_cap = &rv2_res_cap;
res_cap          1286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.res_cap = &res_cap;
res_cap          1300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
res_cap          1497 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
res_cap           221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
res_cap          2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
res_cap          2083 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
res_cap          1316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
res_cap          1347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
res_cap          1365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
res_cap          1372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
res_cap          1541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
res_cap          1548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->res_cap->num_dsc; i++)
res_cap          1562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->res_cap->num_dsc; i++)
res_cap          3020 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	uint32_t pipe_count = pool->res_cap->num_dwb;
res_cap          3045 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	uint32_t pipe_count = pool->res_cap->num_dwb;
res_cap          3424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
res_cap          3450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.res_cap = &res_cap_nv14;
res_cap          3454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.res_cap = &res_cap_nv10;
res_cap          3643 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          3661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
res_cap          3671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
res_cap          3698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
res_cap           844 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
res_cap           875 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap           888 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
res_cap           893 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
res_cap           900 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
res_cap          1280 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
res_cap          1448 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	pool->base.res_cap = &res_cap_rn;
res_cap          1452 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
res_cap          1573 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
res_cap          1591 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
res_cap          1601 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
res_cap          1628 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
res_cap           229 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	const struct resource_caps *res_cap;