req_dppclk         49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		int req_dppclk,
req_dppclk         54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	if (dccg->ref_dppclk && req_dppclk) {
req_dppclk         58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		ASSERT(req_dppclk <= ref_dppclk);
req_dppclk         64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			req_dppclk = (req_dppclk + divider - 1) / divider;
req_dppclk         65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			if (req_dppclk > ref_dppclk)
req_dppclk         66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				req_dppclk = ref_dppclk;
req_dppclk         75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			if (req_dppclk * current_modulo >= current_phase * ref_dppclk) {
req_dppclk         77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 						DPPCLK0_DTO_PHASE, req_dppclk,
req_dppclk         86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 					DPPCLK0_DTO_PHASE, req_dppclk,
req_dppclk        100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
req_dppclk         41 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 			int req_dppclk,