regx               59 arch/alpha/include/asm/spinlock.h 	long regx;
regx               73 arch/alpha/include/asm/spinlock.h 	: "=m" (*lock), "=&r" (regx)
regx               79 arch/alpha/include/asm/spinlock.h 	long regx;
regx               93 arch/alpha/include/asm/spinlock.h 	: "=m" (*lock), "=&r" (regx)
regx               99 arch/alpha/include/asm/spinlock.h 	long regx;
regx              113 arch/alpha/include/asm/spinlock.h 	: "=m" (*lock), "=&r" (regx), "=&r" (success)
regx              121 arch/alpha/include/asm/spinlock.h 	long regx;
regx              135 arch/alpha/include/asm/spinlock.h 	: "=m" (*lock), "=&r" (regx), "=&r" (success)
regx              143 arch/alpha/include/asm/spinlock.h 	long regx;
regx              153 arch/alpha/include/asm/spinlock.h 	: "=m" (*lock), "=&r" (regx)
regx               23 arch/csky/abiv2/fpu.c 	unsigned long instrptr, regx = 0;
regx               54 arch/csky/abiv2/fpu.c 		regx =  *(&regs->a0 + index);
regx               57 arch/csky/abiv2/fpu.c 			mtcr("cr<1, 2>", regx);
regx               59 arch/csky/abiv2/fpu.c 			mtcr("cr<2, 2>", regx);
regx               77 arch/csky/abiv2/fpu.c 			regx = mfcr("cr<1, 2>");
regx               79 arch/csky/abiv2/fpu.c 			regx = mfcr("cr<2, 2>");
regx               83 arch/csky/abiv2/fpu.c 		*(&regs->a0 + index) = regx;
regx             1398 arch/mips/cavium-octeon/octeon-irq.c 	u64 regx, ipx;
regx             1410 arch/mips/cavium-octeon/octeon-irq.c 	for (regx = 0; regx <= 0x8000; regx += 0x1000) {
regx             1412 arch/mips/cavium-octeon/octeon-irq.c 			cvmx_write_csr(base + regx + ipx, 0);
regx              251 sound/x86/intel_hdmi_audio.c 	intelhaddata->aud_config.regx.aud_en = enable;
regx              287 sound/x86/intel_hdmi_audio.c 	ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
regx              289 sound/x86/intel_hdmi_audio.c 	ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
regx              294 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
regx              298 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
regx              301 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
regx              304 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
regx              307 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
regx              310 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
regx              313 sound/x86/intel_hdmi_audio.c 		ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
regx              326 sound/x86/intel_hdmi_audio.c 		ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
regx              327 sound/x86/intel_hdmi_audio.c 		ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
regx              331 sound/x86/intel_hdmi_audio.c 		ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
regx              332 sound/x86/intel_hdmi_audio.c 		ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
regx              357 sound/x86/intel_hdmi_audio.c 	buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
regx              358 sound/x86/intel_hdmi_audio.c 	buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
regx              359 sound/x86/intel_hdmi_audio.c 	buf_cfg.regx.aud_delay = 0;
regx              363 sound/x86/intel_hdmi_audio.c 	cfg_val.regx.num_ch = channels - 2;
regx              365 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.layout = LAYOUT0;
regx              367 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.layout = LAYOUT1;
regx              370 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.packet_mode = 1;
regx              373 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.left_align = 1;
regx              375 sound/x86/intel_hdmi_audio.c 	cfg_val.regx.val_bit = 1;
regx              379 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.dp_modei = 1;
regx              380 sound/x86/intel_hdmi_audio.c 		cfg_val.regx.set = 1;
regx              611 sound/x86/intel_hdmi_audio.c 		frame2.regx.chnl_cnt = substream->runtime->channels - 1;
regx              612 sound/x86/intel_hdmi_audio.c 		frame3.regx.chnl_alloc = ca;
regx              622 sound/x86/intel_hdmi_audio.c 		frame2.regx.chksum = -(checksum);
regx              633 sound/x86/intel_hdmi_audio.c 	ctrl_state.regx.dip_freq = 1;
regx              634 sound/x86/intel_hdmi_audio.c 	ctrl_state.regx.dip_en_sta = 1;
regx              123 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              147 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              166 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              181 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              191 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              203 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              222 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              235 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              247 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              264 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              275 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              293 sound/x86/intel_hdmi_lpe_audio.h 	} regx;
regx              305 sound/x86/intel_hdmi_lpe_audio.h 	} regx;