regp 432 arch/arm64/kernel/cpufeature.c static int search_cmp_ftr_reg(const void *id, const void *regp) regp 434 arch/arm64/kernel/cpufeature.c return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; regp 649 arch/arm64/kernel/cpufeature.c struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); regp 651 arch/arm64/kernel/cpufeature.c BUG_ON(!regp); regp 652 arch/arm64/kernel/cpufeature.c update_cpu_ftr_reg(regp, val); regp 653 arch/arm64/kernel/cpufeature.c if ((boot & regp->strict_mask) == (val & regp->strict_mask)) regp 656 arch/arm64/kernel/cpufeature.c regp->name, boot, cpu, val); regp 802 arch/arm64/kernel/cpufeature.c struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); regp 805 arch/arm64/kernel/cpufeature.c BUG_ON(!regp); regp 806 arch/arm64/kernel/cpufeature.c return regp->sys_val; regp 2163 arch/arm64/kernel/cpufeature.c struct arm64_ftr_reg *regp; regp 2171 arch/arm64/kernel/cpufeature.c regp = get_arm64_ftr_reg(id); regp 2172 arch/arm64/kernel/cpufeature.c if (regp) regp 2173 arch/arm64/kernel/cpufeature.c *valp = arm64_ftr_reg_user_value(regp); regp 731 arch/ia64/kernel/unwind.c spill_next_when (struct unw_reg_info **regp, struct unw_reg_info *lim, unw_word t) regp 735 arch/ia64/kernel/unwind.c for (reg = *regp; reg <= lim; ++reg) { regp 738 arch/ia64/kernel/unwind.c *regp = reg + 1; regp 13 arch/m68k/include/asm/hwtest.h extern int hwreg_present(volatile void *regp); regp 14 arch/m68k/include/asm/hwtest.h extern int hwreg_write(volatile void *regp, unsigned short val); regp 277 arch/m68k/include/asm/oplib.h extern void prom_adjust_regs(struct linux_prom_registers *regp, int nregs, regp 29 arch/m68k/mm/hwtest.c int hwreg_present(volatile void *regp) regp 50 arch/m68k/mm/hwtest.c : "a" (regp), "a" (tmp_vectors) regp 62 arch/m68k/mm/hwtest.c int hwreg_write(volatile void *regp, unsigned short val) regp 87 arch/m68k/mm/hwtest.c : "a" (regp), "a" (tmp_vectors), "g" (val) regp 406 arch/sh/kernel/dwarf.c struct dwarf_reg *regp; regp 429 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); regp 430 arch/sh/kernel/dwarf.c regp->addr = offset; regp 431 arch/sh/kernel/dwarf.c regp->flags |= DWARF_REG_OFFSET; regp 475 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); regp 476 arch/sh/kernel/dwarf.c regp->flags |= DWARF_UNDEFINED; regp 515 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); regp 516 arch/sh/kernel/dwarf.c regp->flags |= DWARF_REG_OFFSET; regp 517 arch/sh/kernel/dwarf.c regp->addr = offset; regp 524 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); regp 525 arch/sh/kernel/dwarf.c regp->flags |= DWARF_VAL_OFFSET; regp 526 arch/sh/kernel/dwarf.c regp->addr = offset; regp 538 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); regp 539 arch/sh/kernel/dwarf.c regp->flags |= DWARF_REG_OFFSET; regp 540 arch/sh/kernel/dwarf.c regp->addr = -offset; regp 20 arch/sparc/prom/ranges.c static void prom_adjust_regs(struct linux_prom_registers *regp, int nregs, regp 27 arch/sparc/prom/ranges.c if (regp[regc].which_io == rangep[rngc].ot_child_space) regp 31 arch/sparc/prom/ranges.c regp[regc].which_io = rangep[rngc].ot_parent_space; regp 32 arch/sparc/prom/ranges.c regp[regc].phys_addr -= rangep[rngc].ot_child_base; regp 33 arch/sparc/prom/ranges.c regp[regc].phys_addr += rangep[rngc].ot_parent_base; regp 312 drivers/edac/pnd2_edac.c #define RD_REGP(regp, regname, port) \ regp 316 drivers/edac/pnd2_edac.c regp, sizeof(struct regname), \ regp 319 drivers/edac/pnd2_edac.c #define RD_REG(regp, regname) \ regp 323 drivers/edac/pnd2_edac.c regp, sizeof(struct regname), \ regp 62 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 64 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; regp 66 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_CSB] = 0x80; regp 67 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; regp 68 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); regp 70 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); regp 77 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 82 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_634 = level; regp 83 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); regp 120 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; regp 121 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nvkm_pll_vals *pv = ®p->pllvals; regp 236 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 303 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg = 0x23; regp 305 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg |= 0x40; regp 307 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg |= 0x80; regp 315 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg = 0xA3; /* +hsync -vsync */ regp 317 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg = 0x63; /* -hsync +vsync */ regp 319 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg = 0xE3; /* -hsync -vsync */ regp 321 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->MiscOutReg = 0x23; /* +hsync +vsync */ regp 327 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; regp 330 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; regp 332 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; regp 333 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; regp 334 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; regp 335 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; regp 340 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; regp 341 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; regp 342 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; regp 343 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | regp 345 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; regp 346 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | regp 348 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; regp 349 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | regp 357 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; regp 358 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | regp 361 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; regp 362 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; regp 363 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; regp 364 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; regp 365 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; regp 366 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; regp 367 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; regp 368 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); regp 369 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; regp 371 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; regp 372 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; regp 373 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; regp 374 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; regp 375 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; regp 376 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; regp 383 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = regp 385 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_42] = regp 387 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? regp 389 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | regp 394 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | regp 398 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | regp 405 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; regp 406 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); regp 408 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ regp 413 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; regp 414 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; regp 415 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; regp 416 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; regp 417 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; regp 418 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ regp 419 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ regp 420 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; regp 421 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; regp 423 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[0] = 0x00; /* standard colormap translation */ regp 424 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[1] = 0x01; regp 425 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[2] = 0x02; regp 426 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[3] = 0x03; regp 427 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[4] = 0x04; regp 428 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[5] = 0x05; regp 429 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[6] = 0x06; regp 430 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[7] = 0x07; regp 431 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[8] = 0x08; regp 432 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[9] = 0x09; regp 433 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[10] = 0x0A; regp 434 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[11] = 0x0B; regp 435 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[12] = 0x0C; regp 436 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[13] = 0x0D; regp 437 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[14] = 0x0E; regp 438 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[15] = 0x0F; regp 439 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ regp 441 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; regp 442 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ regp 443 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; regp 444 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; regp 461 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 489 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); regp 491 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_eng_ctrl = 0; regp 494 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; regp 500 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; regp 505 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | regp 509 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; regp 511 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; regp 514 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_53] = 0; regp 515 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_54] = 0; regp 519 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; regp 521 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; regp 523 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; regp 527 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; regp 537 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; regp 541 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; regp 543 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; regp 547 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; regp 550 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; regp 552 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_830 = mode->crtc_vdisplay - 3; regp 553 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_834 = mode->crtc_vdisplay - 1; regp 557 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); regp 560 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); regp 563 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; regp 565 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; regp 569 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_85] = 0xFF; regp 570 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_86] = 0x1; regp 573 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; regp 576 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); regp 582 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->nv10_cursync = (1 << 25); regp 584 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | regp 588 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; regp 590 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; regp 592 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ regp 593 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->tv_setup = 0; regp 598 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_8c0 = 0x100; regp 599 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_a20 = 0x0; regp 600 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_a24 = 0xfffff; regp 601 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_a34 = 0x1; regp 824 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 856 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; regp 857 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; regp 858 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; regp 860 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; regp 861 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); regp 863 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->ramdac_gen_ctrl); regp 865 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; regp 866 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = regp 868 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_42] = regp 870 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); regp 871 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); regp 872 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); regp 875 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->fb_start = nv_crtc->fb.offset & ~3; regp 876 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); regp 877 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); regp 883 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; regp 884 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; regp 885 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); regp 886 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); regp 889 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; regp 890 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); regp 42 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 45 drivers/gpu/drm/nouveau/dispnv04/cursor.c regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = regp 48 drivers/gpu/drm/nouveau/dispnv04/cursor.c regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = regp 51 drivers/gpu/drm/nouveau/dispnv04/cursor.c regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= regp 53 drivers/gpu/drm/nouveau/dispnv04/cursor.c regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; regp 55 drivers/gpu/drm/nouveau/dispnv04/cursor.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); regp 56 drivers/gpu/drm/nouveau/dispnv04/cursor.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); regp 57 drivers/gpu/drm/nouveau/dispnv04/cursor.c crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); regp 287 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 300 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; regp 301 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; regp 305 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; regp 307 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; regp 308 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; regp 309 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; regp 310 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; regp 311 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; regp 313 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; regp 314 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; regp 315 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; regp 316 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; regp 317 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; regp 318 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_START] = 0; regp 319 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; regp 322 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | regp 327 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; regp 329 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; regp 333 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; regp 336 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; regp 338 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; regp 340 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; regp 343 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= (2 << 24); regp 355 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= (8 << 28); regp 358 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_control |= (8 << 28); regp 360 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | regp 369 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_debug_1 = 0; regp 371 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_debug_2 = 0; regp 389 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | regp 395 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_VALID_START] += diff / 2; regp 396 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; regp 405 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | regp 411 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_START] += diff / 2; regp 412 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_END] -= diff / 2; regp 421 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither = savep->dither | 0x00010000; regp 424 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither = savep->dither | 0x00000001; regp 426 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither_regs[i] = 0xe4e4e4e4; regp 427 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither_regs[i + 3] = 0x44444444; regp 435 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither_regs[i] = savep->dither_regs[i]; regp 436 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither_regs[i + 3] = savep->dither_regs[i + 3]; regp 439 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->dither = savep->dither; regp 442 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_margin_color = 0; regp 395 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 399 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); regp 401 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); regp 406 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); regp 408 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); regp 411 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); regp 413 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); regp 415 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); regp 416 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); regp 417 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); regp 418 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); regp 419 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); regp 420 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); regp 421 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); regp 422 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); regp 426 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); regp 427 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); regp 431 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); regp 433 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); regp 434 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); regp 438 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); regp 439 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); regp 443 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & regp 446 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); regp 447 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); regp 449 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); regp 452 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); regp 455 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); regp 456 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); regp 457 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); regp 460 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->ctv_regs[i] = NVReadRAMDAC(dev, head, regp 471 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 476 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); regp 478 drivers/gpu/drm/nouveau/dispnv04/hw.c clk->pll_prog(clk, pllreg, ®p->pllvals); regp 483 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); regp 485 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); regp 488 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); regp 490 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); regp 492 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); regp 493 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); regp 494 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); regp 495 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); regp 496 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); regp 497 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); regp 498 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); regp 499 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); regp 504 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); regp 505 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); regp 509 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); regp 511 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); regp 512 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); regp 516 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); regp 517 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); regp 518 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); regp 519 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); regp 521 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); regp 524 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); regp 527 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); regp 528 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); regp 529 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); regp 533 drivers/gpu/drm/nouveau/dispnv04/hw.c NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); regp 541 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 544 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); regp 547 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, i); regp 551 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->Attribute[i] = NVReadVgaAttr(dev, head, i); regp 555 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->Graphics[i] = NVReadVgaGr(dev, head, i); regp 558 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); regp 565 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 568 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); regp 571 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); regp 575 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, i); regp 579 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteVgaGr(dev, head, i, regp->Graphics[i]); regp 583 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); regp 592 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 595 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); regp 596 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); regp 597 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); regp 598 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); regp 599 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); regp 600 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); regp 601 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); regp 603 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); regp 604 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); regp 605 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_21); regp 608 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_47); regp 611 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, 0x9f); regp 613 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_49); regp 614 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); regp 615 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); regp 616 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); regp 617 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); regp 620 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); regp 621 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); regp 624 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); regp 627 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); regp 630 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); regp 631 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); regp 634 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); regp 636 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); regp 637 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); regp 639 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); regp 640 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); regp 641 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); regp 642 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); regp 646 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_42); regp 647 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_53); regp 648 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_54); regp 651 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); regp 652 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_59); regp 653 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); regp 655 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_85); regp 656 drivers/gpu/drm/nouveau/dispnv04/hw.c rd_cio_state(dev, head, regp, NV_CIO_CRE_86); regp 659 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); regp 668 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nv04_crtc_reg *regp = &state->crtc_reg[head]; regp 678 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); regp 690 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); regp 691 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); regp 692 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); regp 695 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); regp 698 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); regp 701 drivers/gpu/drm/nouveau/dispnv04/hw.c if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) regp 708 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); regp 710 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); regp 711 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); regp 712 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); regp 713 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); regp 714 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); regp 715 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); regp 716 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); regp 717 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); regp 718 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); regp 721 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_47); regp 724 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, 0x9f); regp 726 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_49); regp 727 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); regp 728 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); regp 729 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); regp 732 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); regp 734 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); regp 735 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); regp 737 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); regp 738 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); regp 739 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); regp 740 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); regp 757 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_42); regp 758 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_53); regp 759 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_54); regp 762 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); regp 763 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_59); regp 764 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); regp 766 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_85); regp 767 drivers/gpu/drm/nouveau/dispnv04/hw.c wr_cio_state(dev, head, regp, NV_CIO_CRE_86); regp 770 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); regp 146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; regp 148 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_htotal = adjusted_mode->htotal; regp 149 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_vtotal = adjusted_mode->vtotal; regp 155 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_hskew = 1; regp 156 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_hsync_delay = 1; regp 157 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_hsync_delay2 = 64; regp 158 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_vskew = 1; regp 159 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c regp->tv_vsync_delay = 1; regp 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; regp 110 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wr32(device, c->regp, 0x00000000); regp 12 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h unsigned regp; regp 1009 drivers/hwmon/lm90.c struct reg *regp = ®[index]; regp 1026 drivers/hwmon/lm90.c err = i2c_smbus_write_byte_data(client, regp->high, regp 1031 drivers/hwmon/lm90.c err = i2c_smbus_write_byte_data(client, regp->low, regp 3766 drivers/hwmon/nct6775.c static void add_temp_sensors(struct nct6775_data *data, const u16 *regp, regp 3775 drivers/hwmon/nct6775.c if (!regp[i]) regp 3777 drivers/hwmon/nct6775.c src = nct6775_read_value(data, regp[i]); regp 495 drivers/mfd/ab3100-core.c int regp; regp 514 drivers/mfd/ab3100-core.c regp = i; regp 525 drivers/mfd/ab3100-core.c err = kstrtou8(&buf[regp], 16, &user_reg); regp 407 drivers/net/ethernet/amd/atarilance.c static noinline int __init addr_accessible(volatile void *regp, int wordflag, regp 446 drivers/net/ethernet/amd/atarilance.c : "a" (regp), "a" (&vbr[2]), "rm" (wordflag), "rm" (writeflag) regp 270 drivers/video/fbdev/bw2.c u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; regp 271 drivers/video/fbdev/bw2.c sbus_writeb(p[1], regp); regp 336 drivers/video/fbdev/cg3.c u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; regp 337 drivers/video/fbdev/cg3.c sbus_writeb(p[1], regp); regp 340 drivers/video/fbdev/cg3.c u8 __iomem *regp; regp 342 drivers/video/fbdev/cg3.c regp = (u8 __iomem *)&par->regs->cmap.addr; regp 343 drivers/video/fbdev/cg3.c sbus_writeb(p[0], regp); regp 344 drivers/video/fbdev/cg3.c regp = (u8 __iomem *)&par->regs->cmap.control; regp 345 drivers/video/fbdev/cg3.c sbus_writeb(p[1], regp);