reg_volt         1588 drivers/clk/tegra/clk-dfll.c 	unsigned long rate, reg_volt;
reg_volt         1593 drivers/clk/tegra/clk-dfll.c 		reg_volt = td->lut_uv[i];
reg_volt         1596 drivers/clk/tegra/clk-dfll.c 		reg_volt = (reg_volt / 1000) * 1000;
reg_volt         1597 drivers/clk/tegra/clk-dfll.c 		if (reg_volt > v_max)
reg_volt         1601 drivers/clk/tegra/clk-dfll.c 		if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))