reg_vals 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); reg_vals 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); reg_vals 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); reg_vals 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); reg_vals 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); reg_vals 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_log_pps(dsc, &dsc20->reg_vals.pps); reg_vals 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_write_to_registers(dsc, &dsc20->reg_vals); reg_vals 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) reg_vals 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c memset(reg_vals, 0, sizeof(struct dsc_reg_values)); reg_vals 453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->dsc_clock_enable = 1; reg_vals 454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->dsc_clock_gating_disable = 0; reg_vals 455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->underflow_recovery_en = 0; reg_vals 456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->underflow_occurred_int_en = 0; reg_vals 457 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->underflow_occurred_status = 0; reg_vals 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->ich_reset_at_eol = 0; reg_vals 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->alternate_ich_encoding_en = 0; reg_vals 460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->rc_buffer_model_size = 0; reg_vals 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->dsc_dbg_en = 0; reg_vals 465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->rc_buffer_model_overflow_int_en[i] = 0; reg_vals 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.dsc_version_minor = 2; reg_vals 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.dsc_version_major = 1; reg_vals 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.line_buf_depth = 9; reg_vals 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.bits_per_component = 8; reg_vals 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.block_pred_enable = 1; reg_vals 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_chunk_size = 0; reg_vals 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.pic_width = 0; reg_vals 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.pic_height = 0; reg_vals 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_width = 0; reg_vals 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_height = 0; reg_vals 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_xmit_delay = 170; reg_vals 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_dec_delay = 0; reg_vals 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_scale_value = 0; reg_vals 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.scale_increment_interval = 0; reg_vals 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.scale_decrement_interval = 0; reg_vals 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.nfl_bpg_offset = 0; reg_vals 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_bpg_offset = 0; reg_vals 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.nsl_bpg_offset = 0; reg_vals 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_offset = 6144; reg_vals 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.final_offset = 0; reg_vals 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.flatness_min_qp = 3; reg_vals 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.flatness_max_qp = 12; reg_vals 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_model_size = 8192; reg_vals 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_edge_factor = 6; reg_vals 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_quant_incr_limit0 = 11; reg_vals 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_quant_incr_limit1 = 11; reg_vals 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_tgt_offset_low = 3; reg_vals 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_tgt_offset_high = 3; reg_vals 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) reg_vals 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps = dsc_params->pps; reg_vals 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; reg_vals 512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; reg_vals 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; reg_vals 516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) reg_vals 522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSC_DBG_EN, reg_vals->dsc_dbg_en); reg_vals 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, reg_vals 527 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, reg_vals 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, reg_vals 529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INPUT_PIXEL_FORMAT, reg_vals->pixel_format, reg_vals 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); reg_vals 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_WIDTH, reg_vals->pps.pic_width, reg_vals 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_HEIGHT, reg_vals->pps.pic_height); reg_vals 538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, reg_vals 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, reg_vals 540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, reg_vals 541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); reg_vals 544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); reg_vals 550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], reg_vals 551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], reg_vals 552 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], reg_vals 553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); reg_vals 556 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, reg_vals 557 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, reg_vals 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); reg_vals 560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) reg_vals 561 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c temp_int = reg_vals->bpp_x32; reg_vals 563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c temp_int = reg_vals->bpp_x32 >> 1; reg_vals 567 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, reg_vals 568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, reg_vals 569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, reg_vals 570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, reg_vals 571 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, reg_vals 572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c CHUNK_SIZE, reg_vals->pps.slice_chunk_size); reg_vals 575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_WIDTH, reg_vals->pps.pic_width, reg_vals 576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_HEIGHT, reg_vals->pps.pic_height); reg_vals 579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_WIDTH, reg_vals->pps.slice_width, reg_vals 580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_HEIGHT, reg_vals->pps.slice_height); reg_vals 583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); reg_vals 586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, reg_vals 587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); reg_vals 590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, reg_vals 591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, reg_vals 592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); reg_vals 595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, reg_vals 596 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); reg_vals 599 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, reg_vals 600 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); reg_vals 603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_OFFSET, reg_vals->pps.initial_offset, reg_vals 604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FINAL_OFFSET, reg_vals->pps.final_offset); reg_vals 607 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, reg_vals 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, reg_vals 609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_MODEL_SIZE, reg_vals->pps.rc_model_size); reg_vals 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, reg_vals 613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, reg_vals 614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, reg_vals 615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, reg_vals 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); reg_vals 619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], reg_vals 620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], reg_vals 621 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], reg_vals 622 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); reg_vals 625 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], reg_vals 626 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], reg_vals 627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], reg_vals 628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); reg_vals 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], reg_vals 632 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], reg_vals 633 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], reg_vals 634 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); reg_vals 637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], reg_vals 638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], reg_vals 639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, reg_vals 640 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, reg_vals 641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); reg_vals 644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, reg_vals 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, reg_vals 646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, reg_vals 647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, reg_vals 648 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, reg_vals 649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); reg_vals 652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, reg_vals 653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, reg_vals 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, reg_vals 655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, reg_vals 656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, reg_vals 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); reg_vals 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, reg_vals 661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, reg_vals 662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, reg_vals 663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, reg_vals 664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, reg_vals 665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); reg_vals 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, reg_vals 669 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, reg_vals 670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, reg_vals 671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, reg_vals 672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, reg_vals 673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); reg_vals 676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, reg_vals 677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, reg_vals 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, reg_vals 679 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, reg_vals 680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, reg_vals 681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); reg_vals 684 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, reg_vals 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, reg_vals 686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, reg_vals 687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, reg_vals 688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, reg_vals 689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); reg_vals 692 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, reg_vals 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, reg_vals 694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, reg_vals 695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, reg_vals 696 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, reg_vals 697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); reg_vals 709 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c temp_int = reg_vals->pps.initial_dec_delay; reg_vals 560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h struct dsc_reg_values reg_vals; reg_vals 974 drivers/infiniband/hw/qib/qib_sd7220.c uint8_t reg_vals[NUM_DDS_REGS]; reg_vals 1076 drivers/infiniband/hw/qib/qib_sd7220.c data = dds_init_vals[midx].reg_vals[idx]; reg_vals 1201 drivers/infiniband/hw/qib/qib_sd7220.c data = ddi->reg_vals[idx]; reg_vals 95 drivers/media/dvb-frontends/ts2020.c static const struct ts2020_reg_val reg_vals[] = { reg_vals 137 drivers/media/dvb-frontends/ts2020.c for (i = 0; i < ARRAY_SIZE(reg_vals); i++) reg_vals 138 drivers/media/dvb-frontends/ts2020.c regmap_write(priv->regmap, reg_vals[i].reg, reg_vals 139 drivers/media/dvb-frontends/ts2020.c reg_vals[i].val); reg_vals 588 drivers/media/tuners/m88rs6000t.c static const struct m88rs6000t_reg_val reg_vals[] = { reg_vals 680 drivers/media/tuners/m88rs6000t.c for (i = 0; i < ARRAY_SIZE(reg_vals); i++) { reg_vals 682 drivers/media/tuners/m88rs6000t.c reg_vals[i].reg, reg_vals[i].val);