reg_val_lvl       159 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift;
reg_val_lvl       170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high);
reg_val_lvl       177 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val_lvl &= ~mask;
reg_val_lvl       178 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	reg_val_lvl |= (remap_level << reg_shift) & mask;
reg_val_lvl       181 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 	DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl);