reg_val32          71 arch/mips/pci/fixup-malta.c 	u32 reg_val32;
reg_val32         104 arch/mips/pci/fixup-malta.c 	pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
reg_val32         106 arch/mips/pci/fixup-malta.c 			       reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);