reg_sq_cmd        491 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union SQ_CMD_BITS reg_sq_cmd;
reg_sq_cmd        495 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.u32All = 0;
reg_sq_cmd        506 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.check_vmid = 1;
reg_sq_cmd        507 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD;
reg_sq_cmd        508 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId;
reg_sq_cmd        509 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE;
reg_sq_cmd        524 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
reg_sq_cmd        531 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.check_vmid = 1;
reg_sq_cmd        532 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
reg_sq_cmd        546 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT;
reg_sq_cmd        550 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME;
reg_sq_cmd        554 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
reg_sq_cmd        558 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG;
reg_sq_cmd        563 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 			reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP;
reg_sq_cmd        564 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 			reg_sq_cmd.bits.trap_id = wac_info->trapId;
reg_sq_cmd        576 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		*in_reg_sq_cmd = reg_sq_cmd;
reg_sq_cmd        588 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union SQ_CMD_BITS reg_sq_cmd;
reg_sq_cmd        595 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.u32All = 0;
reg_sq_cmd        597 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	status = dbgdev_wave_control_set_registers(wac_info, &reg_sq_cmd,
reg_sq_cmd        605 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.bits.vm_id = 0;
reg_sq_cmd        616 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);
reg_sq_cmd        617 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);
reg_sq_cmd        618 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);
reg_sq_cmd        619 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);
reg_sq_cmd        620 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);
reg_sq_cmd        621 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);
reg_sq_cmd        622 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);
reg_sq_cmd        665 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;
reg_sq_cmd        701 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union SQ_CMD_BITS reg_sq_cmd;
reg_sq_cmd        705 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.u32All = 0;
reg_sq_cmd        714 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	status = dbgdev_wave_control_set_registers(wac_info, &reg_sq_cmd,
reg_sq_cmd        723 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.bits.vm_id = pdd->qpd.vmid;
reg_sq_cmd        734 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);
reg_sq_cmd        735 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);
reg_sq_cmd        736 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);
reg_sq_cmd        737 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);
reg_sq_cmd        738 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);
reg_sq_cmd        739 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);
reg_sq_cmd        740 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);
reg_sq_cmd        757 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 							reg_sq_cmd.u32All);
reg_sq_cmd        764 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union SQ_CMD_BITS reg_sq_cmd;
reg_sq_cmd        771 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.u32All = 0;
reg_sq_cmd        806 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	status = dbgdev_wave_control_set_registers(&wac_info, &reg_sq_cmd,
reg_sq_cmd        812 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	reg_sq_cmd.bits.vm_id = vmid;
reg_sq_cmd        816 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 					reg_sq_cmd.u32All);