reg_region_cur 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t reg_region_cur; reg_region_cur 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (reg_region_cur = reg->region_start; reg_region_cur 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg_region_cur <= reg->region_end; reg_region_cur 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg_region_cur++) { reg_region_cur 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_4(reg_region_cur, 0,