reg_ofs           140 arch/arm/mach-bcm/platsmp-brcmstb.c 	const int reg_ofs = cpu_logical_map(cpu) * 8;
reg_ofs           141 arch/arm/mach-bcm/platsmp-brcmstb.c 	writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
reg_ofs           142 arch/arm/mach-bcm/platsmp-brcmstb.c 	writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
reg_ofs           227 drivers/clk/clk-cdce925.c 	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
reg_ofs           233 drivers/clk/clk-cdce925.c 			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
reg_ofs           262 drivers/clk/clk-cdce925.c 				reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
reg_ofs           265 drivers/clk/clk-cdce925.c 			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
reg_ofs           274 drivers/clk/clk-cdce925.c 	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
reg_ofs           277 drivers/clk/clk-cdce925.c 			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
reg_ofs          1007 drivers/clk/mediatek/clk-mt8173.c 	u32 reg_ofs;
reg_ofs          1014 drivers/clk/mediatek/clk-mt8173.c 		.reg_ofs = _reg_ofs,					\
reg_ofs          1103 drivers/clk/mediatek/clk-mt8173.c 					base + cku->reg_ofs);
reg_ofs           241 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	const unsigned int *reg_ofs;
reg_ofs           322 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
reg_ofs           327 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
reg_ofs           451 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	.reg_ofs = exynos_reg_ofs,
reg_ofs           463 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	.reg_ofs = exynos_reg_ofs,
reg_ofs           475 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	.reg_ofs = exynos_reg_ofs,
reg_ofs           485 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	.reg_ofs = exynos5433_reg_ofs,
reg_ofs           496 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	.reg_ofs = exynos5433_reg_ofs,
reg_ofs            56 drivers/gpu/drm/stm/ltdc.c #define REG_OFS		(ldev->caps.reg_ofs)
reg_ofs          1091 drivers/gpu/drm/stm/ltdc.c 		ldev->caps.reg_ofs = REG_OFS_NONE;
reg_ofs          1106 drivers/gpu/drm/stm/ltdc.c 		ldev->caps.reg_ofs = REG_OFS_4;
reg_ofs            17 drivers/gpu/drm/stm/ltdc.h 	u32 reg_ofs;		/* register offset for applicable regs */
reg_ofs           132 drivers/staging/vt6656/mac.c int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits)
reg_ofs           139 drivers/staging/vt6656/mac.c 	return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs,
reg_ofs           143 drivers/staging/vt6656/mac.c int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits)
reg_ofs           150 drivers/staging/vt6656/mac.c 	return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs,
reg_ofs           154 drivers/staging/vt6656/mac.c void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word)
reg_ofs           161 drivers/staging/vt6656/mac.c 	vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs,
reg_ofs           363 drivers/staging/vt6656/mac.h int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
reg_ofs           364 drivers/staging/vt6656/mac.h int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
reg_ofs           365 drivers/staging/vt6656/mac.h void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);