reg_offsets 49 arch/nios2/kernel/misaligned.c static int reg_offsets[32]; reg_offsets 53 arch/nios2/kernel/misaligned.c u8 *p = ((u8 *)fp) + reg_offsets[reg]; reg_offsets 59 arch/nios2/kernel/misaligned.c u8 *p = ((u8 *)fp) + reg_offsets[reg]; reg_offsets 214 arch/nios2/kernel/misaligned.c reg_offsets[r] = offset; reg_offsets 222 arch/nios2/kernel/misaligned.c reg_offsets[r] = offset; reg_offsets 55 arch/x86/um/ptrace_32.c static const int reg_offsets[] = { reg_offsets 120 arch/x86/um/ptrace_32.c child->thread.regs.regs.gp[reg_offsets[regno]] = value; reg_offsets 172 arch/x86/um/ptrace_32.c return mask & child->thread.regs.regs.gp[reg_offsets[regno]]; reg_offsets 22 arch/x86/um/ptrace_64.c static const int reg_offsets[] = reg_offsets 114 arch/x86/um/ptrace_64.c child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value; reg_offsets 178 arch/x86/um/ptrace_64.c return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]]; reg_offsets 44 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { reg_offsets 66 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c (reg + reg_offsets[id].crtc) reg_offsets 47 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c static const struct dce110_compressor_reg_offsets reg_offsets[] = { reg_offsets 81 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c cp110->offsets = reg_offsets[crtc_inst]; reg_offsets 307 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c cp110->offsets = reg_offsets[params->inst]; reg_offsets 89 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { reg_offsets 105 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (reg + reg_offsets[id].blnd) reg_offsets 108 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (reg + reg_offsets[id].crtc) reg_offsets 46 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c static const struct dce112_compressor_reg_offsets reg_offsets[] = { reg_offsets 405 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c cp110->offsets = reg_offsets[params->inst]; reg_offsets 42 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { reg_offsets 63 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c (reg + reg_offsets[id].crtc) reg_offsets 53 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c static const struct dce120_hw_seq_reg_offsets reg_offsets[] = { reg_offsets 75 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c (reg + reg_offsets[id].crtc) reg_offsets 43 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { reg_offsets 65 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c (reg + reg_offsets[id].crtc) reg_offsets 51 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c static const struct dce110_timing_generator_offsets reg_offsets[] = { reg_offsets 233 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->derived_offsets = reg_offsets[instance]; reg_offsets 776 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; reg_offsets 473 drivers/gpu/drm/msm/adreno/a2xx_gpu.c adreno_gpu->reg_offsets = a2xx_register_offsets; reg_offsets 489 drivers/gpu/drm/msm/adreno/a3xx_gpu.c adreno_gpu->reg_offsets = a3xx_register_offsets; reg_offsets 573 drivers/gpu/drm/msm/adreno/a4xx_gpu.c adreno_gpu->reg_offsets = a4xx_register_offsets; reg_offsets 1442 drivers/gpu/drm/msm/adreno/a5xx_gpu.c adreno_gpu->reg_offsets = a5xx_register_offsets; reg_offsets 865 drivers/gpu/drm/msm/adreno/a6xx_gpu.c adreno_gpu->reg_offsets = a6xx_register_offsets; reg_offsets 125 drivers/gpu/drm/msm/adreno/adreno_gpu.h const unsigned int *reg_offsets; reg_offsets 319 drivers/gpu/drm/msm/adreno/adreno_gpu.h !gpu->reg_offsets[offset_name]) { reg_offsets 329 drivers/gpu/drm/msm/adreno/adreno_gpu.h if (gpu->reg_offsets[offset_name] == REG_SKIP) reg_offsets 338 drivers/gpu/drm/msm/adreno/adreno_gpu.h u32 reg = gpu->reg_offsets[offset_name]; reg_offsets 348 drivers/gpu/drm/msm/adreno/adreno_gpu.h u32 reg = gpu->reg_offsets[offset_name]; reg_offsets 127 drivers/i2c/busses/i2c-mv64xxx.c struct mv64xxx_i2c_regs reg_offsets; reg_offsets 214 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); reg_offsets 216 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.clock); reg_offsets 217 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); reg_offsets 218 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); reg_offsets 220 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 342 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 370 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 375 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_offsets 377 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 382 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_offsets 384 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 389 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_offsets 391 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 396 drivers/i2c/busses/i2c-mv64xxx.c readl(drv_data->reg_base + drv_data->reg_offsets.data); reg_offsets 398 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 403 drivers/i2c/busses/i2c-mv64xxx.c readl(drv_data->reg_base + drv_data->reg_offsets.data); reg_offsets 406 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 425 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 509 drivers/i2c/busses/i2c-mv64xxx.c while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & reg_offsets 511 drivers/i2c/busses/i2c-mv64xxx.c status = readl(drv_data->reg_base + drv_data->reg_offsets.status); reg_offsets 517 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_offsets 840 drivers/i2c/busses/i2c-mv64xxx.c memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); reg_offsets 923 drivers/i2c/busses/i2c-mv64xxx.c memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets)); reg_offsets 191 drivers/mtd/nand/raw/brcmnand/brcmnand.c const u16 *reg_offsets; reg_offsets 518 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets = brcmnand_regs_v72; reg_offsets 520 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets = brcmnand_regs_v71; reg_offsets 522 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets = brcmnand_regs_v60; reg_offsets 524 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets = brcmnand_regs_v50; reg_offsets 526 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets = brcmnand_regs_v40; reg_offsets 607 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs = ctrl->reg_offsets[reg]; reg_offsets 618 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs = ctrl->reg_offsets[reg]; reg_offsets 697 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; reg_offsets 698 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; reg_offsets 1204 drivers/mtd/nand/raw/brcmnand/brcmnand.c offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; reg_offsets 1205 drivers/mtd/nand/raw/brcmnand/brcmnand.c offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; reg_offsets 1223 drivers/mtd/nand/raw/brcmnand/brcmnand.c offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; reg_offsets 1224 drivers/mtd/nand/raw/brcmnand/brcmnand.c offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; reg_offsets 2606 drivers/mtd/nand/raw/brcmnand/brcmnand.c ctrl->reg_offsets[BRCMNAND_FC_BASE]; reg_offsets 982 drivers/net/dsa/bcm_sf2.c const u16 *reg_offsets; reg_offsets 1007 drivers/net/dsa/bcm_sf2.c .reg_offsets = bcm_sf2_7445_reg_offsets, reg_offsets 1030 drivers/net/dsa/bcm_sf2.c .reg_offsets = bcm_sf2_7278_reg_offsets, reg_offsets 1089 drivers/net/dsa/bcm_sf2.c priv->reg_offsets = data->reg_offsets; reg_offsets 69 drivers/net/dsa/bcm_sf2.h const u16 *reg_offsets; reg_offsets 187 drivers/net/dsa/bcm_sf2.h return readl_relaxed(priv->reg + priv->reg_offsets[off]); reg_offsets 192 drivers/net/dsa/bcm_sf2.h writel_relaxed(val, priv->reg + priv->reg_offsets[off]); reg_offsets 95 drivers/net/ethernet/8390/ax88796.c u32 reg_offsets[0x20]; reg_offsets 887 drivers/net/ethernet/8390/ax88796.c if (ax->plat->reg_offsets) reg_offsets 888 drivers/net/ethernet/8390/ax88796.c ei_local->reg_offset = ax->plat->reg_offsets; reg_offsets 890 drivers/net/ethernet/8390/ax88796.c ei_local->reg_offset = ax->reg_offsets; reg_offsets 892 drivers/net/ethernet/8390/ax88796.c ax->reg_offsets[ret] = (mem_size / 0x18) * ret; reg_offsets 914 drivers/net/ethernet/8390/ax88796.c if (!ax->plat->reg_offsets) { reg_offsets 916 drivers/net/ethernet/8390/ax88796.c ax->reg_offsets[ret] = (mem_size / 0x20) * ret; reg_offsets 259 drivers/net/ethernet/8390/xsurf100.c static u32 reg_offsets[32]; reg_offsets 282 drivers/net/ethernet/8390/xsurf100.c reg_offsets[reg] = 4 * reg; reg_offsets 289 drivers/net/ethernet/8390/xsurf100.c ax88796_data.ax.reg_offsets = reg_offsets; reg_offsets 142 drivers/pci/controller/dwc/pcie-al.c struct al_pcie_reg_offsets reg_offsets; reg_offsets 196 drivers/pci/controller/dwc/pcie-al.c pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET; reg_offsets 200 drivers/pci/controller/dwc/pcie-al.c pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET; reg_offsets 221 drivers/pci/controller/dwc/pcie-al.c pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS, reg_offsets 327 drivers/pci/controller/dwc/pcie-al.c cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + reg_offsets 95 drivers/pci/controller/pcie-iproc-msi.c const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE]; reg_offsets 134 drivers/pci/controller/pcie-iproc-msi.c return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); reg_offsets 143 drivers/pci/controller/pcie-iproc-msi.c writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); reg_offsets 563 drivers/pci/controller/pcie-iproc-msi.c msi->reg_offsets = iproc_msi_reg_paxb; reg_offsets 568 drivers/pci/controller/pcie-iproc-msi.c msi->reg_offsets = iproc_msi_reg_paxc; reg_offsets 413 drivers/pci/controller/pcie-iproc.c return pcie->reg_offsets[reg]; reg_offsets 1470 drivers/pci/controller/pcie-iproc.c pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, reg_offsets 1471 drivers/pci/controller/pcie-iproc.c sizeof(*pcie->reg_offsets), reg_offsets 1473 drivers/pci/controller/pcie-iproc.c if (!pcie->reg_offsets) reg_offsets 1477 drivers/pci/controller/pcie-iproc.c pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? reg_offsets 1480 drivers/pci/controller/pcie-iproc.c pcie->reg_offsets[reg_idx] = regs[reg_idx] ? reg_offsets 84 drivers/pci/controller/pcie-iproc.h u16 *reg_offsets; reg_offsets 140 drivers/spi/spi-bcm63xx.c const unsigned long *reg_offsets; reg_offsets 156 drivers/spi/spi-bcm63xx.c return readb(bs->regs + bs->reg_offsets[offset]); reg_offsets 163 drivers/spi/spi-bcm63xx.c return ioread16be(bs->regs + bs->reg_offsets[offset]); reg_offsets 165 drivers/spi/spi-bcm63xx.c return readw(bs->regs + bs->reg_offsets[offset]); reg_offsets 172 drivers/spi/spi-bcm63xx.c writeb(value, bs->regs + bs->reg_offsets[offset]); reg_offsets 179 drivers/spi/spi-bcm63xx.c iowrite16be(value, bs->regs + bs->reg_offsets[offset]); reg_offsets 181 drivers/spi/spi-bcm63xx.c writew(value, bs->regs + bs->reg_offsets[offset]); reg_offsets 553 drivers/spi/spi-bcm63xx.c bs->reg_offsets = bcm63xx_spireg; reg_offsets 554 drivers/spi/spi-bcm63xx.c bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; reg_offsets 572 drivers/spi/spi-bcm63xx.c bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; reg_offsets 573 drivers/spi/spi-bcm63xx.c bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; reg_offsets 574 drivers/spi/spi-bcm63xx.c bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]); reg_offsets 575 drivers/spi/spi-bcm63xx.c bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]); reg_offsets 26 include/net/ax88796.h u32 *reg_offsets; /* register offsets */