reg_offset 41 arch/arm/mach-omap2/hsmmc.c mmc->reg_offset = 0; reg_offset 69 arch/arm/mach-rockchip/pm.c static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, reg_offset 78 arch/arm/mach-rockchip/pm.c for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { reg_offset 79 arch/arm/mach-rockchip/pm.c regmap_read(grf_regmap, reg_offset[i], ®); reg_offset 59 arch/powerpc/boot/ns16550.c u32 reg_offset; reg_offset 64 arch/powerpc/boot/ns16550.c n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset)); reg_offset 65 arch/powerpc/boot/ns16550.c if (n == sizeof(reg_offset)) reg_offset 66 arch/powerpc/boot/ns16550.c reg_base += reg_offset; reg_offset 28 arch/powerpc/boot/virtex.c u32 reg_shift, reg_offset, clk, spd; reg_offset 35 arch/powerpc/boot/virtex.c n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset)); reg_offset 36 arch/powerpc/boot/virtex.c if (n == sizeof(reg_offset)) reg_offset 37 arch/powerpc/boot/virtex.c reg_base += reg_offset; reg_offset 103 arch/powerpc/include/asm/tsi108.h static inline u32 tsi108_read_reg(u32 reg_offset) reg_offset 105 arch/powerpc/include/asm/tsi108.h return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset)); reg_offset 108 arch/powerpc/include/asm/tsi108.h static inline void tsi108_write_reg(u32 reg_offset, u32 val) reg_offset 110 arch/powerpc/include/asm/tsi108.h out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); reg_offset 44 arch/powerpc/sysdev/tsi108_pci.c extern u32 tsi108_read_reg(u32 reg_offset); reg_offset 45 arch/powerpc/sysdev/tsi108_pci.c extern void tsi108_write_reg(u32 reg_offset, u32 val); reg_offset 44 arch/x86/include/asm/uprobes.h u8 reg_offset; /* to the start of pt_regs */ reg_offset 320 arch/x86/kernel/umip.c int not_copied, nr_copied, reg_offset, dummy_data_size, umip_inst; reg_offset 403 arch/x86/kernel/umip.c reg_offset = insn_get_modrm_rm_off(&insn, regs); reg_offset 410 arch/x86/kernel/umip.c if (reg_offset < 0) reg_offset 413 arch/x86/kernel/umip.c reg_addr = (unsigned long *)((unsigned long)regs + reg_offset); reg_offset 664 arch/x86/kernel/uprobes.c unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset; reg_offset 765 arch/x86/kernel/uprobes.c u8 opc1 = OPCODE1(insn), reg_offset = 0; reg_offset 781 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r8); reg_offset 784 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r9); reg_offset 787 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r10); reg_offset 790 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r11); reg_offset 793 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r12); reg_offset 796 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r13); reg_offset 799 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r14); reg_offset 802 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, r15); reg_offset 811 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, ax); reg_offset 814 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, cx); reg_offset 817 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, dx); reg_offset 820 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, bx); reg_offset 823 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, sp); reg_offset 826 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, bp); reg_offset 829 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, si); reg_offset 832 arch/x86/kernel/uprobes.c reg_offset = offsetof(struct pt_regs, di); reg_offset 837 arch/x86/kernel/uprobes.c auprobe->push.reg_offset = reg_offset; reg_offset 32 arch/x86/math-emu/get_address.c static int reg_offset[] = { reg_offset 43 arch/x86/math-emu/get_address.c #define REG_(x) (*(long *)(reg_offset[(x)] + (u_char *)FPU_info->regs)) reg_offset 105 drivers/base/regmap/regmap-debugfs.c unsigned int reg_offset; reg_offset 168 drivers/base/regmap/regmap-debugfs.c reg_offset = fpos_offset / map->debugfs_tot_len; reg_offset 169 drivers/base/regmap/regmap-debugfs.c *pos = c->min + (reg_offset * map->debugfs_tot_len); reg_offset 171 drivers/base/regmap/regmap-debugfs.c return c->base_reg + (reg_offset * map->reg_stride); reg_offset 233 drivers/base/regmap/regmap-irq.c mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; reg_offset 240 drivers/base/regmap/regmap-irq.c d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; reg_offset 249 drivers/base/regmap/regmap-irq.c d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; reg_offset 307 drivers/base/regmap/regmap-irq.c d->wake_buf[irq_data->reg_offset / map->reg_stride] reg_offset 312 drivers/base/regmap/regmap-irq.c d->wake_buf[irq_data->reg_offset / map->reg_stride] reg_offset 504 drivers/base/regmap/regmap-irq.c if (data->status_buf[chip->irqs[i].reg_offset / reg_offset 577 drivers/base/regmap/regmap-irq.c if (chip->irqs[i].reg_offset % map->reg_stride) reg_offset 579 drivers/base/regmap/regmap-irq.c if (chip->irqs[i].reg_offset / map->reg_stride >= reg_offset 670 drivers/base/regmap/regmap-irq.c d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] reg_offset 130 drivers/clk/bcm/clk-kona.c static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) reg_offset 132 drivers/clk/bcm/clk-kona.c return readl(ccu->base + reg_offset); reg_offset 137 drivers/clk/bcm/clk-kona.c __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) reg_offset 139 drivers/clk/bcm/clk-kona.c writel(reg_val, ccu->base + reg_offset); reg_offset 191 drivers/clk/bcm/clk-kona.c __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want) reg_offset 200 drivers/clk/bcm/clk-kona.c val = __ccu_read(ccu, reg_offset); reg_offset 207 drivers/clk/bcm/clk-kona.c ccu->name, reg_offset, bit, want ? "set" : "clear"); reg_offset 265 drivers/clk/nxp/clk-lpc18xx-cgu.c u8 reg_offset; reg_offset 276 drivers/clk/nxp/clk-lpc18xx-cgu.c .reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \ reg_offset 589 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; reg_offset 590 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; reg_offset 72 drivers/clk/qcom/apcs-msm8916.c a53cc->reg_offset = 0x50; reg_offset 33 drivers/clk/qcom/clk-regmap-mux-div.c ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset, reg_offset 38 drivers/clk/qcom/clk-regmap-mux-div.c ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset, reg_offset 45 drivers/clk/qcom/clk-regmap-mux-div.c ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, reg_offset 65 drivers/clk/qcom/clk-regmap-mux-div.c regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val); reg_offset 72 drivers/clk/qcom/clk-regmap-mux-div.c regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val); reg_offset 28 drivers/clk/qcom/clk-regmap-mux-div.h u32 reg_offset; reg_offset 55 drivers/clk/ti/clkctrl.c u16 reg_offset; reg_offset 242 drivers/clk/ti/clkctrl.c if (entry->reg_offset == clkspec->args[0] && reg_offset 291 drivers/clk/ti/clkctrl.c clkctrl_clk->reg_offset = offset; reg_offset 630 drivers/clk/ti/clkctrl.c clkctrl_clk->reg_offset = reg_data->offset; reg_offset 59 drivers/clocksource/timer-atmel-pit.c static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset) reg_offset 61 drivers/clocksource/timer-atmel-pit.c return readl_relaxed(base + reg_offset); reg_offset 64 drivers/clocksource/timer-atmel-pit.c static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value) reg_offset 66 drivers/clocksource/timer-atmel-pit.c writel_relaxed(value, base + reg_offset); reg_offset 577 drivers/crypto/cavium/zip/zip_main.c zipregs[i].reg_offset)); reg_offset 68 drivers/crypto/cavium/zip/zip_main.h u64 reg_offset; reg_offset 894 drivers/crypto/hisilicon/qm.c u64 reg_offset; reg_offset 944 drivers/crypto/hisilicon/qm.c val = readl(qm->io_base + regs->reg_offset); reg_offset 1835 drivers/crypto/hisilicon/qm.c readl(qm->io_base + regs->reg_offset); reg_offset 167 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADC, }, reg_offset 168 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADCERROR, }, reg_offset 169 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADC1K, }, reg_offset 172 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_CHGTYP, }, reg_offset 173 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_CHGDETRUN, }, reg_offset 174 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_DCDTMR, }, reg_offset 175 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_DXOVP, }, reg_offset 176 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_VBVOLT, }, reg_offset 179 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_VBADC, }, reg_offset 180 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_VDNMON, }, reg_offset 181 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_DNRES, }, reg_offset 182 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MPNACK, }, reg_offset 183 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXBUFOW, }, reg_offset 184 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXTRF, }, reg_offset 185 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXPERR, }, reg_offset 186 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXRDY, }, reg_offset 172 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_ATTACH_MASK, }, reg_offset 173 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_DETACH_MASK, }, reg_offset 174 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_CHGDET_MASK, }, reg_offset 175 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_DCD_T_MASK, }, reg_offset 176 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_OVP_MASK, }, reg_offset 177 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_CONNECT_MASK, }, reg_offset 178 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_ADC_CHG_MASK, }, reg_offset 179 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_OTP_MASK, }, reg_offset 182 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_UVLOT_MASK,}, reg_offset 183 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_POR_MASK, }, reg_offset 184 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OTP_FET_MASK, }, reg_offset 185 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OVP_FET_MASK, }, reg_offset 186 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OCP_LATCH_MASK, }, reg_offset 187 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OCP_MASK, }, reg_offset 188 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OVP_OCP_MASK, }, reg_offset 173 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, }, reg_offset 174 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, }, reg_offset 175 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, }, reg_offset 176 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, }, reg_offset 177 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, }, reg_offset 178 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, }, reg_offset 179 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, }, reg_offset 180 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, }, reg_offset 183 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,}, reg_offset 184 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_REV_ACCE_MASK, }, reg_offset 185 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_ADC_CHG_MASK, }, reg_offset 186 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_MASK, }, reg_offset 187 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK, }, reg_offset 188 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_MHL_MASK, }, reg_offset 134 drivers/fpga/socfpga.c static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) reg_offset 136 drivers/fpga/socfpga.c return readl(priv->fpga_base_addr + reg_offset); reg_offset 139 drivers/fpga/socfpga.c static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, reg_offset 142 drivers/fpga/socfpga.c writel(value, priv->fpga_base_addr + reg_offset); reg_offset 146 drivers/fpga/socfpga.c u32 reg_offset) reg_offset 148 drivers/fpga/socfpga.c return __raw_readl(priv->fpga_base_addr + reg_offset); reg_offset 152 drivers/fpga/socfpga.c u32 reg_offset, u32 value) reg_offset 154 drivers/fpga/socfpga.c __raw_writel(value, priv->fpga_base_addr + reg_offset); reg_offset 139 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; reg_offset 150 drivers/gpio/gpio-bcm-kona.c reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); reg_offset 152 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_offset 154 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); reg_offset 166 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; reg_offset 174 drivers/gpio/gpio-bcm-kona.c reg_offset = GPIO_IN_STATUS(bank_id); reg_offset 176 drivers/gpio/gpio-bcm-kona.c reg_offset = GPIO_OUT_STATUS(bank_id); reg_offset 179 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_offset 230 drivers/gpio/gpio-bcm-kona.c u32 val, reg_offset; reg_offset 241 drivers/gpio/gpio-bcm-kona.c reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); reg_offset 243 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_offset 245 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); reg_offset 87 drivers/gpio/gpio-lynxpoint.c int reg_offset; reg_offset 91 drivers/gpio/gpio-lynxpoint.c reg_offset = offset * 8; reg_offset 94 drivers/gpio/gpio-lynxpoint.c reg_offset = (offset / 32) * 4; reg_offset 96 drivers/gpio/gpio-lynxpoint.c return lg->reg_base + reg + reg_offset; reg_offset 28 drivers/gpio/gpio-madera.c unsigned int reg_offset = 2 * offset; reg_offset 32 drivers/gpio/gpio-madera.c ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_2 + reg_offset, reg_offset 44 drivers/gpio/gpio-madera.c unsigned int reg_offset = 2 * offset; reg_offset 47 drivers/gpio/gpio-madera.c MADERA_GPIO1_CTRL_2 + reg_offset, reg_offset 55 drivers/gpio/gpio-madera.c unsigned int reg_offset = 2 * offset; reg_offset 59 drivers/gpio/gpio-madera.c ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_1 + reg_offset, reg_offset 72 drivers/gpio/gpio-madera.c unsigned int reg_offset = 2 * offset; reg_offset 77 drivers/gpio/gpio-madera.c MADERA_GPIO1_CTRL_2 + reg_offset, reg_offset 83 drivers/gpio/gpio-madera.c MADERA_GPIO1_CTRL_1 + reg_offset, reg_offset 92 drivers/gpio/gpio-madera.c unsigned int reg_offset = 2 * offset; reg_offset 97 drivers/gpio/gpio-madera.c MADERA_GPIO1_CTRL_1 + reg_offset, reg_offset 103 drivers/gpio/gpio-madera.c MADERA_GPIO1_CTRL_1 + reg_offset, ret); reg_offset 25 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 36 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 47 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 58 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 69 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 80 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 91 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 102 drivers/gpio/gpio-max77620.c .reg_offset = 0, reg_offset 104 drivers/gpio/gpio-uniphier.c unsigned int bank, reg_offset; reg_offset 108 drivers/gpio/gpio-uniphier.c reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; reg_offset 110 drivers/gpio/gpio-uniphier.c return !!(readl(priv->regs + reg_offset) & mask); reg_offset 262 drivers/gpio/gpio-zynq.c unsigned int reg_offset, bank_num, bank_pin_num; reg_offset 270 drivers/gpio/gpio-zynq.c reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); reg_offset 272 drivers/gpio/gpio-zynq.c reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); reg_offset 283 drivers/gpio/gpio-zynq.c writel_relaxed(state, gpio->base_addr + reg_offset); reg_offset 533 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t reg_offset; reg_offset 553 drivers/gpu/drm/amd/amdgpu/amdgpu.h u32 sh_num, u32 reg_offset, u32 *value); reg_offset 674 drivers/gpu/drm/amd/amdgpu/amdgpu.h u32 reg_offset; reg_offset 976 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; reg_offset 109 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); reg_offset 111 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA1_HWIP][0][1] + offset); reg_offset 113 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); reg_offset 115 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); reg_offset 117 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); reg_offset 119 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); reg_offset 121 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); reg_offset 123 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); reg_offset 99 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c unsigned int reg_offset); reg_offset 908 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c unsigned int reg_offset) reg_offset 134 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c unsigned int reg_offset); reg_offset 756 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c unsigned int reg_offset) reg_offset 758 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; reg_offset 90 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c unsigned int reg_offset); reg_offset 735 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c unsigned int reg_offset) reg_offset 775 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c unsigned int reg_offset) reg_offset 56 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h unsigned int reg_offset); reg_offset 322 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c adev->reg_offset[hw_ip][ip->number_instance] = reg_offset 1052 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c offset[1] = adev->reg_offset[UVD_HWIP][0][1]; reg_offset 1053 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c offset[2] = adev->reg_offset[UVD_HWIP][1][1]; reg_offset 63 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ reg_offset 75 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ reg_offset 85 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg_offset 35 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i])); reg_offset 51 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i])); reg_offset 52 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i])); reg_offset 53 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 54 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 1029 drivers/gpu/drm/amd/amdgpu/cik.c u32 sh_num, u32 reg_offset) reg_offset 1036 drivers/gpu/drm/amd/amdgpu/cik.c switch (reg_offset) { reg_offset 1051 drivers/gpu/drm/amd/amdgpu/cik.c val = RREG32(reg_offset); reg_offset 1060 drivers/gpu/drm/amd/amdgpu/cik.c switch (reg_offset) { reg_offset 1097 drivers/gpu/drm/amd/amdgpu/cik.c idx = (reg_offset - mmGB_TILE_MODE0); reg_offset 1115 drivers/gpu/drm/amd/amdgpu/cik.c idx = (reg_offset - mmGB_MACROTILE_MODE0); reg_offset 1118 drivers/gpu/drm/amd/amdgpu/cik.c return RREG32(reg_offset); reg_offset 1124 drivers/gpu/drm/amd/amdgpu/cik.c u32 sh_num, u32 reg_offset, u32 *value) reg_offset 1132 drivers/gpu/drm/amd/amdgpu/cik.c if (reg_offset != cik_allowed_read_registers[i].reg_offset) reg_offset 1136 drivers/gpu/drm/amd/amdgpu/cik.c reg_offset); reg_offset 400 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 reg_offset, split_equal_to_row_size, *tilemode; reg_offset 640 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 641 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); reg_offset 846 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 847 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); reg_offset 1070 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1071 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); reg_offset 1294 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1295 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); reg_offset 1029 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 reg_offset, split_equal_to_row_size; reg_offset 1048 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1049 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c tile[reg_offset] = 0; reg_offset 1050 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 1051 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c macrotile[reg_offset] = 0; reg_offset 1215 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1216 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); reg_offset 1217 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 1218 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (reg_offset != 7) reg_offset 1219 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); reg_offset 1398 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1399 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); reg_offset 1400 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 1401 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (reg_offset != 7) reg_offset 1402 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); reg_offset 1568 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 1569 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); reg_offset 1570 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 1571 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (reg_offset != 7) reg_offset 1572 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); reg_offset 2130 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 reg_offset; reg_offset 2135 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2136 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c modearray[reg_offset] = 0; reg_offset 2138 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2139 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mod2array[reg_offset] = 0; reg_offset 2303 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2304 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && reg_offset 2305 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c reg_offset != 23) reg_offset 2306 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 2308 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2309 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 2310 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 2495 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2496 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 2498 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2499 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 2500 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 2684 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2685 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 2687 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2688 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 2689 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 2887 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2888 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 2890 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2891 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 2892 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 3089 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 3090 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 3092 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 3093 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 3094 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 3258 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 3259 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && reg_offset 3260 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c reg_offset != 23) reg_offset 3261 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 3263 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 3264 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 3265 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 3435 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 3436 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && reg_offset 3437 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c reg_offset != 23) reg_offset 3438 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); reg_offset 3440 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 3441 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (reg_offset != 7) reg_offset 3442 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); reg_offset 5756 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t reg_offset; reg_offset 6125 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->reg_offset[gfx_ras_edc_regs[i].ip] reg_offset 6128 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_ras_edc_regs[i].reg_offset); reg_offset 1404 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u16 reg_offset, u32 value) reg_offset 1408 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, reg_offset 1413 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u16 reg_offset, u32 *value) reg_offset 1417 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset, reg_offset 51 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset : 28; reg_offset 56 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset : 20; reg_offset 89 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, reg_offset 92 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_wt->cmd_header.reg_offset = reg_offset; reg_offset 99 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, reg_offset 102 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; reg_offset 111 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t reg_offset, reg_offset 114 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_poll->cmd_header.reg_offset = reg_offset; reg_offset 35 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); reg_offset 35 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); reg_offset 35 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); reg_offset 41 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); reg_offset 67 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); reg_offset 69 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); reg_offset 56 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); reg_offset 58 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); reg_offset 84 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); reg_offset 86 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); reg_offset 185 drivers/gpu/drm/amd/amdgpu/nv.c u32 sh_num, u32 reg_offset) reg_offset 193 drivers/gpu/drm/amd/amdgpu/nv.c val = RREG32(reg_offset); reg_offset 203 drivers/gpu/drm/amd/amdgpu/nv.c u32 sh_num, u32 reg_offset) reg_offset 206 drivers/gpu/drm/amd/amdgpu/nv.c return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); reg_offset 208 drivers/gpu/drm/amd/amdgpu/nv.c if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) reg_offset 210 drivers/gpu/drm/amd/amdgpu/nv.c return RREG32(reg_offset); reg_offset 215 drivers/gpu/drm/amd/amdgpu/nv.c u32 sh_num, u32 reg_offset, u32 *value) reg_offset 223 drivers/gpu/drm/amd/amdgpu/nv.c if (reg_offset != reg_offset 224 drivers/gpu/drm/amd/amdgpu/nv.c (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) reg_offset 229 drivers/gpu/drm/amd/amdgpu/nv.c se_num, sh_num, reg_offset); reg_offset 617 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; reg_offset 618 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; reg_offset 628 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; reg_offset 629 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; reg_offset 265 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); reg_offset 267 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); reg_offset 269 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); reg_offset 271 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); reg_offset 273 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); reg_offset 275 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); reg_offset 277 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); reg_offset 279 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); reg_offset 112 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c base = adev->reg_offset[GC_HWIP][0][1]; reg_offset 116 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c base = adev->reg_offset[GC_HWIP][0][0]; reg_offset 1414 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? reg_offset 1418 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_cntl = RREG32(reg_offset); reg_offset 1421 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(reg_offset, sdma_cntl); reg_offset 1019 drivers/gpu/drm/amd/amdgpu/si.c u32 sh_num, u32 reg_offset) reg_offset 1026 drivers/gpu/drm/amd/amdgpu/si.c switch (reg_offset) { reg_offset 1039 drivers/gpu/drm/amd/amdgpu/si.c val = RREG32(reg_offset); reg_offset 1048 drivers/gpu/drm/amd/amdgpu/si.c switch (reg_offset) { reg_offset 1085 drivers/gpu/drm/amd/amdgpu/si.c idx = (reg_offset - mmGB_TILE_MODE0); reg_offset 1088 drivers/gpu/drm/amd/amdgpu/si.c return RREG32(reg_offset); reg_offset 1093 drivers/gpu/drm/amd/amdgpu/si.c u32 sh_num, u32 reg_offset, u32 *value) reg_offset 1101 drivers/gpu/drm/amd/amdgpu/si.c if (reg_offset != si_allowed_read_registers[i].reg_offset) reg_offset 1105 drivers/gpu/drm/amd/amdgpu/si.c reg_offset); reg_offset 1845 drivers/gpu/drm/amd/amdgpu/si_dpm.c u16 reg_offset, u32 value); reg_offset 3644 drivers/gpu/drm/amd/amdgpu/si_dpm.c u16 reg_offset, u32 *value) reg_offset 3649 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, value, reg_offset 3655 drivers/gpu/drm/amd/amdgpu/si_dpm.c u16 reg_offset, u32 value) reg_offset 3660 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, reg_offset 372 drivers/gpu/drm/amd/amdgpu/soc15.c u32 sh_num, u32 reg_offset) reg_offset 380 drivers/gpu/drm/amd/amdgpu/soc15.c val = RREG32(reg_offset); reg_offset 390 drivers/gpu/drm/amd/amdgpu/soc15.c u32 sh_num, u32 reg_offset) reg_offset 393 drivers/gpu/drm/amd/amdgpu/soc15.c return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); reg_offset 395 drivers/gpu/drm/amd/amdgpu/soc15.c if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) reg_offset 397 drivers/gpu/drm/amd/amdgpu/soc15.c else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) reg_offset 399 drivers/gpu/drm/amd/amdgpu/soc15.c return RREG32(reg_offset); reg_offset 404 drivers/gpu/drm/amd/amdgpu/soc15.c u32 sh_num, u32 reg_offset, u32 *value) reg_offset 412 drivers/gpu/drm/amd/amdgpu/soc15.c if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] reg_offset 413 drivers/gpu/drm/amd/amdgpu/soc15.c + en->reg_offset)) reg_offset 418 drivers/gpu/drm/amd/amdgpu/soc15.c se_num, sh_num, reg_offset); reg_offset 446 drivers/gpu/drm/amd/amdgpu/soc15.c reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; reg_offset 1010 drivers/gpu/drm/amd/amdgpu/soc15.c adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; reg_offset 49 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t reg_offset; reg_offset 59 drivers/gpu/drm/amd/amdgpu/soc15.h uint32_t reg_offset; reg_offset 65 drivers/gpu/drm/amd/amdgpu/soc15.h #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) reg_offset 28 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) reg_offset 31 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ reg_offset 32 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ reg_offset 36 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) reg_offset 39 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) reg_offset 42 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) reg_offset 45 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) reg_offset 48 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) reg_offset 53 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg_offset 62 drivers/gpu/drm/amd/amdgpu/soc15_common.h tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg_offset 79 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ reg_offset 80 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ reg_offset 81 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ reg_offset 100 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ reg_offset 102 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ reg_offset 103 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ reg_offset 104 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ reg_offset 105 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ reg_offset 118 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ reg_offset 123 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ reg_offset 124 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ reg_offset 128 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) reg_offset 1274 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c reg -= p->adev->reg_offset[UVD_HWIP][0][1]; reg_offset 1275 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c reg += p->adev->reg_offset[UVD_HWIP][1][1]; reg_offset 1939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); reg_offset 1951 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || reg_offset 1952 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { reg_offset 1955 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); reg_offset 1957 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg_offset); reg_offset 1983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); reg_offset 1987 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || reg_offset 1988 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { reg_offset 1991 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); reg_offset 1993 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg_offset); reg_offset 2012 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) reg_offset 2016 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || reg_offset 2017 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { reg_offset 2019 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); reg_offset 2021 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[(*ptr)++] = reg_offset; reg_offset 2031 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, reg_offset, val, mask, i; reg_offset 2035 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2037 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 2041 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2043 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 2053 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2055 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 2059 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2061 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 2065 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2074 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || reg_offset 2075 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { reg_offset 2077 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); reg_offset 2079 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = reg_offset; reg_offset 2092 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2094 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 2098 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg_offset 2100 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); reg_offset 1990 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); reg_offset 2002 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { reg_offset 2005 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); reg_offset 2007 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg_offset); reg_offset 2031 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); reg_offset 2035 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { reg_offset 2038 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); reg_offset 2040 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg_offset); reg_offset 35 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 51 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); reg_offset 52 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i])); reg_offset 53 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 54 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); reg_offset 35 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); reg_offset 36 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); reg_offset 37 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); reg_offset 38 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); reg_offset 39 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); reg_offset 40 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); reg_offset 41 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); reg_offset 42 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); reg_offset 43 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); reg_offset 44 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); reg_offset 45 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); reg_offset 46 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); reg_offset 47 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); reg_offset 48 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); reg_offset 49 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); reg_offset 50 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); reg_offset 51 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); reg_offset 52 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); reg_offset 53 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); reg_offset 54 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i])); reg_offset 553 drivers/gpu/drm/amd/amdgpu/vi.c u32 sh_num, u32 reg_offset) reg_offset 560 drivers/gpu/drm/amd/amdgpu/vi.c switch (reg_offset) { reg_offset 575 drivers/gpu/drm/amd/amdgpu/vi.c val = RREG32(reg_offset); reg_offset 584 drivers/gpu/drm/amd/amdgpu/vi.c switch (reg_offset) { reg_offset 621 drivers/gpu/drm/amd/amdgpu/vi.c idx = (reg_offset - mmGB_TILE_MODE0); reg_offset 639 drivers/gpu/drm/amd/amdgpu/vi.c idx = (reg_offset - mmGB_MACROTILE_MODE0); reg_offset 642 drivers/gpu/drm/amd/amdgpu/vi.c return RREG32(reg_offset); reg_offset 648 drivers/gpu/drm/amd/amdgpu/vi.c u32 sh_num, u32 reg_offset, u32 *value) reg_offset 656 drivers/gpu/drm/amd/amdgpu/vi.c if (reg_offset != vi_allowed_read_registers[i].reg_offset) reg_offset 660 drivers/gpu/drm/amd/amdgpu/vi.c reg_offset); reg_offset 427 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[0].bitfields2.reg_offset = reg_offset 438 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[1].bitfields2.reg_offset = reg_offset 448 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[2].bitfields2.reg_offset = reg_offset 464 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[3].bitfields2.reg_offset = reg_offset 652 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[0].bitfields2.reg_offset = reg_offset 661 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE; reg_offset 676 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c packets_vec[2].bitfields2.reg_offset = reg_offset 190 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h unsigned int reg_offset:16; reg_offset 293 drivers/gpu/drm/amd/include/kgd_kfd_interface.h unsigned int reg_offset); reg_offset 93 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] reg_offset 94 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c + entry[i].reg_offset; reg_offset 41 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t reg_offset; reg_offset 290 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 reg_offset = (master_pipe == 0) ? reg_offset 293 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL); reg_offset 565 drivers/gpu/drm/exynos/exynos_drm_g2d.c static enum g2d_reg_type g2d_get_reg_type(struct g2d_data *g2d, int reg_offset) reg_offset 569 drivers/gpu/drm/exynos/exynos_drm_g2d.c switch (reg_offset) { reg_offset 599 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_offset); reg_offset 1025 drivers/gpu/drm/exynos/exynos_drm_g2d.c int reg_offset; reg_offset 1037 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_offset = cmdlist->data[index] & ~0xfffff000; reg_offset 1038 drivers/gpu/drm/exynos/exynos_drm_g2d.c if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END) reg_offset 1040 drivers/gpu/drm/exynos/exynos_drm_g2d.c if (reg_offset % 4) reg_offset 1043 drivers/gpu/drm/exynos/exynos_drm_g2d.c switch (reg_offset) { reg_offset 1053 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_type = g2d_get_reg_type(g2d, reg_offset); reg_offset 1067 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_type = g2d_get_reg_type(g2d, reg_offset); reg_offset 1077 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_type = g2d_get_reg_type(g2d, reg_offset); reg_offset 1089 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_type = g2d_get_reg_type(g2d, reg_offset); reg_offset 1102 drivers/gpu/drm/exynos/exynos_drm_g2d.c reg_type = g2d_get_reg_type(g2d, reg_offset); reg_offset 715 drivers/gpu/drm/exynos/exynos_hdmi.c u32 reg_offset, const u8 *buf, u32 len) reg_offset 717 drivers/gpu/drm/exynos/exynos_hdmi.c if ((reg_offset + len) > 32) reg_offset 731 drivers/gpu/drm/exynos/exynos_hdmi.c ((reg_offset + i)<<2)); reg_offset 254 drivers/gpu/drm/gma500/intel_gmbus.c int i, reg_offset; reg_offset 260 drivers/gpu/drm/gma500/intel_gmbus.c reg_offset = 0; reg_offset 262 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0); reg_offset 269 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS1 + reg_offset, reg_offset 275 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); reg_offset 279 drivers/gpu/drm/gma500/intel_gmbus.c if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & reg_offset 282 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) reg_offset 285 drivers/gpu/drm/gma500/intel_gmbus.c val = GMBUS_REG_READ(GMBUS3 + reg_offset); reg_offset 299 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); reg_offset 300 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS1 + reg_offset, reg_offset 305 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); reg_offset 308 drivers/gpu/drm/gma500/intel_gmbus.c if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & reg_offset 311 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & reg_offset 320 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); reg_offset 321 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); reg_offset 325 drivers/gpu/drm/gma500/intel_gmbus.c if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) reg_offset 327 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) reg_offset 338 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); reg_offset 339 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0); reg_offset 345 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); reg_offset 351 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); reg_offset 42 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 reg_offset; reg_offset 87 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ reg_offset 96 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ reg_offset 725 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl->reg_offset = ctl_cfg->base[c]; reg_offset 152 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c uint32_t reg_offset, uint32_t caps) reg_offset 162 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c hwpipe->reg_offset = reg_offset; reg_offset 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t reg_offset; reg_offset 43 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t reg_offset, uint32_t caps); reg_offset 1282 drivers/gpu/drm/radeon/ci_dpm.c u16 reg_offset, u32 *value) reg_offset 1287 drivers/gpu/drm/radeon/ci_dpm.c pi->soft_regs_start + reg_offset, reg_offset 1293 drivers/gpu/drm/radeon/ci_dpm.c u16 reg_offset, u32 value) reg_offset 1298 drivers/gpu/drm/radeon/ci_dpm.c pi->soft_regs_start + reg_offset, reg_offset 2341 drivers/gpu/drm/radeon/cik.c u32 reg_offset, split_equal_to_row_size; reg_offset 2363 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2364 drivers/gpu/drm/radeon/cik.c tile[reg_offset] = 0; reg_offset 2365 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2366 drivers/gpu/drm/radeon/cik.c macrotile[reg_offset] = 0; reg_offset 2506 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2507 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 2508 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2509 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); reg_offset 2649 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2650 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 2651 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2652 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); reg_offset 2874 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2875 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 2876 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 2877 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); reg_offset 3017 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 3018 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 3019 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) reg_offset 3020 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); reg_offset 252 drivers/gpu/drm/radeon/cik_sdma.c u32 rb_cntl, reg_offset; reg_offset 261 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA0_REGISTER_OFFSET; reg_offset 263 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; reg_offset 264 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); reg_offset 266 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); reg_offset 267 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); reg_offset 306 drivers/gpu/drm/radeon/cik_sdma.c uint32_t reg_offset, value; reg_offset 311 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA0_REGISTER_OFFSET; reg_offset 313 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; reg_offset 314 drivers/gpu/drm/radeon/cik_sdma.c value = RREG32(SDMA0_CNTL + reg_offset); reg_offset 319 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_CNTL + reg_offset, value); reg_offset 333 drivers/gpu/drm/radeon/cik_sdma.c u32 me_cntl, reg_offset; reg_offset 343 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA0_REGISTER_OFFSET; reg_offset 345 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; reg_offset 346 drivers/gpu/drm/radeon/cik_sdma.c me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); reg_offset 351 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); reg_offset 370 drivers/gpu/drm/radeon/cik_sdma.c u32 reg_offset, wb_offset; reg_offset 376 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA0_REGISTER_OFFSET; reg_offset 380 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; reg_offset 384 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); reg_offset 385 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); reg_offset 393 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); reg_offset 396 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); reg_offset 397 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); reg_offset 400 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, reg_offset 402 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, reg_offset 408 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); reg_offset 409 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); reg_offset 412 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); reg_offset 415 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); reg_offset 422 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); reg_offset 1336 drivers/gpu/drm/radeon/kv_dpm.c u16 reg_offset, u32 value) reg_offset 1340 drivers/gpu/drm/radeon/kv_dpm.c return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, reg_offset 1345 drivers/gpu/drm/radeon/kv_dpm.c u16 reg_offset, u32 *value) reg_offset 1349 drivers/gpu/drm/radeon/kv_dpm.c return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, reg_offset 192 drivers/gpu/drm/radeon/ni_dma.c u32 reg_offset, wb_offset; reg_offset 198 drivers/gpu/drm/radeon/ni_dma.c reg_offset = DMA0_REGISTER_OFFSET; reg_offset 202 drivers/gpu/drm/radeon/ni_dma.c reg_offset = DMA1_REGISTER_OFFSET; reg_offset 206 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); reg_offset 207 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); reg_offset 215 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); reg_offset 218 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR + reg_offset, 0); reg_offset 219 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_WPTR + reg_offset, 0); reg_offset 222 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, reg_offset 224 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, reg_offset 230 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); reg_offset 237 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); reg_offset 239 drivers/gpu/drm/radeon/ni_dma.c dma_cntl = RREG32(DMA_CNTL + reg_offset); reg_offset 241 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_CNTL + reg_offset, dma_cntl); reg_offset 244 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); reg_offset 246 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); reg_offset 235 drivers/gpu/drm/radeon/rv770_dpm.c u16 reg_offset, u32 *value) reg_offset 240 drivers/gpu/drm/radeon/rv770_dpm.c pi->soft_regs_start + reg_offset, reg_offset 246 drivers/gpu/drm/radeon/rv770_dpm.c u16 reg_offset, u32 value) reg_offset 251 drivers/gpu/drm/radeon/rv770_dpm.c pi->soft_regs_start + reg_offset, reg_offset 283 drivers/gpu/drm/radeon/rv770_dpm.h u16 reg_offset, u32 value); reg_offset 2498 drivers/gpu/drm/radeon/si.c u32 reg_offset, split_equal_to_row_size; reg_offset 2513 drivers/gpu/drm/radeon/si.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2514 drivers/gpu/drm/radeon/si.c tile[reg_offset] = 0; reg_offset 2727 drivers/gpu/drm/radeon/si.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2728 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 2942 drivers/gpu/drm/radeon/si.c for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) reg_offset 2943 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); reg_offset 1754 drivers/gpu/drm/radeon/si_dpm.c u16 reg_offset, u32 value); reg_offset 3185 drivers/gpu/drm/radeon/si_dpm.c u16 reg_offset, u32 *value) reg_offset 3190 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, value, reg_offset 3196 drivers/gpu/drm/radeon/si_dpm.c u16 reg_offset, u32 value) reg_offset 3201 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, reg_offset 79 drivers/gpu/host1x/hw/syncpt_hw.c u32 reg_offset = sp->id / 32; reg_offset 86 drivers/gpu/host1x/hw/syncpt_hw.c HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset)); reg_offset 681 drivers/i2c/busses/i2c-tegra.c unsigned long reg_offset; reg_offset 687 drivers/i2c/busses/i2c-tegra.c reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); reg_offset 688 drivers/i2c/busses/i2c-tegra.c addr = i2c_dev->base + reg_offset; reg_offset 940 drivers/i2c/busses/i2c-tegra.c unsigned long reg_offset; reg_offset 957 drivers/i2c/busses/i2c-tegra.c reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); reg_offset 958 drivers/i2c/busses/i2c-tegra.c slv_config.src_addr = i2c_dev->base_phys + reg_offset; reg_offset 968 drivers/i2c/busses/i2c-tegra.c reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); reg_offset 969 drivers/i2c/busses/i2c-tegra.c slv_config.dst_addr = i2c_dev->base_phys + reg_offset; reg_offset 77 drivers/input/keyboard/omap4-keypad.c u32 reg_offset; reg_offset 88 drivers/input/keyboard/omap4-keypad.c keypad_data->reg_offset + offset); reg_offset 94 drivers/input/keyboard/omap4-keypad.c keypad_data->base + keypad_data->reg_offset + offset); reg_offset 290 drivers/input/keyboard/omap4-keypad.c keypad_data->reg_offset = 0x00; reg_offset 294 drivers/input/keyboard/omap4-keypad.c keypad_data->reg_offset = 0x10; reg_offset 78 drivers/input/touchscreen/edt-ft5x06.c int reg_offset; reg_offset 629 drivers/input/touchscreen/edt-ft5x06.c if (reg_addr->reg_offset != NO_REGISTER) reg_offset 630 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, reg_offset 938 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, val); reg_offset 963 drivers/input/touchscreen/edt-ft5x06.c if (reg_addr->reg_offset != NO_REGISTER) reg_offset 965 drivers/input/touchscreen/edt-ft5x06.c edt_ft5x06_register_read(tsdata, reg_addr->reg_offset); reg_offset 998 drivers/input/touchscreen/edt-ft5x06.c reg_addr->reg_offset = WORK_REGISTER_OFFSET; reg_offset 1010 drivers/input/touchscreen/edt-ft5x06.c reg_addr->reg_offset = M09_REGISTER_OFFSET; reg_offset 1020 drivers/input/touchscreen/edt-ft5x06.c reg_addr->reg_offset = NO_REGISTER; reg_offset 1032 drivers/input/touchscreen/edt-ft5x06.c reg_addr->reg_offset = M09_REGISTER_OFFSET; reg_offset 24 drivers/irqchip/irq-bcm2836.c static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset, reg_offset 28 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; reg_offset 33 drivers/irqchip/irq-bcm2836.c static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset, reg_offset 37 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; reg_offset 26 drivers/irqchip/irq-madera.c .reg_offset = (_reg) - MADERA_IRQ1_STATUS_2, \ reg_offset 148 drivers/leds/leds-bd2802.c u8 reg_offset) reg_offset 150 drivers/leds/leds-bd2802.c return reg_offset + bd2802_get_base_offset(id, color); reg_offset 278 drivers/media/platform/omap3isp/isp.h u32 reg_offset) reg_offset 280 drivers/media/platform/omap3isp/isp.h return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); reg_offset 292 drivers/media/platform/omap3isp/isp.h enum isp_mem_resources isp_mmio_range, u32 reg_offset) reg_offset 294 drivers/media/platform/omap3isp/isp.h __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); reg_offset 61 drivers/memory/pl172.c u32 reg_offset, u32 max, int start) reg_offset 76 drivers/memory/pl172.c writel(cycles, pl172->base + reg_offset); reg_offset 80 drivers/memory/pl172.c readl(pl172->base + reg_offset)); reg_offset 47 drivers/memory/samsung/exynos-srom.c struct exynos_srom_reg_dump *reg_offset; reg_offset 132 drivers/memory/samsung/exynos-srom.c srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets, reg_offset 134 drivers/memory/samsung/exynos-srom.c if (!srom->reg_offset) { reg_offset 179 drivers/memory/samsung/exynos-srom.c exynos_srom_save(srom->reg_base, srom->reg_offset, reg_offset 188 drivers/memory/samsung/exynos-srom.c exynos_srom_restore(srom->reg_base, srom->reg_offset, reg_offset 189 drivers/mfd/88pm800.c .reg_offset = 1, reg_offset 193 drivers/mfd/88pm800.c .reg_offset = 1, reg_offset 197 drivers/mfd/88pm800.c .reg_offset = 1, reg_offset 201 drivers/mfd/88pm800.c .reg_offset = 1, reg_offset 206 drivers/mfd/88pm800.c .reg_offset = 2, reg_offset 210 drivers/mfd/88pm800.c .reg_offset = 2, reg_offset 214 drivers/mfd/88pm800.c .reg_offset = 2, reg_offset 218 drivers/mfd/88pm800.c .reg_offset = 2, reg_offset 222 drivers/mfd/88pm800.c .reg_offset = 2, reg_offset 227 drivers/mfd/88pm800.c .reg_offset = 3, reg_offset 231 drivers/mfd/88pm800.c .reg_offset = 3, reg_offset 235 drivers/mfd/88pm800.c .reg_offset = 3, reg_offset 239 drivers/mfd/88pm800.c .reg_offset = 3, reg_offset 243 drivers/mfd/88pm800.c .reg_offset = 3, reg_offset 111 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 115 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 119 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 123 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 127 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 131 drivers/mfd/88pm805.c .reg_offset = 1, reg_offset 99 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 103 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 107 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 111 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 115 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 119 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 123 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 127 drivers/mfd/as3722.c .reg_offset = 1, reg_offset 133 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 137 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 141 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 145 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 149 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 153 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 157 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 161 drivers/mfd/as3722.c .reg_offset = 2, reg_offset 167 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 171 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 175 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 179 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 183 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 187 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 191 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 195 drivers/mfd/as3722.c .reg_offset = 3, reg_offset 284 drivers/mfd/axp20x.c [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } reg_offset 36 drivers/mfd/cs47l24-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 37 drivers/mfd/cs47l24-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 40 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 reg_offset 43 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 reg_offset 46 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 reg_offset 49 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 reg_offset 52 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 reg_offset 55 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 reg_offset 58 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 reg_offset 61 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 reg_offset 64 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 reg_offset 67 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 reg_offset 71 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 74 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 77 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 80 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 reg_offset 83 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 86 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 reg_offset 89 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 reg_offset 92 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 95 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 98 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 101 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 104 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 107 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 111 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 reg_offset 114 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 117 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 120 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 reg_offset 123 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 reg_offset 126 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 reg_offset 129 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 reg_offset 132 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 reg_offset 135 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 reg_offset 139 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 142 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 reg_offset 145 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 148 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 152 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 reg_offset 155 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 reg_offset 158 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 reg_offset 161 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 reg_offset 164 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 reg_offset 167 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 reg_offset 37 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 41 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 45 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 49 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 53 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 57 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 61 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 65 drivers/mfd/da9052-irq.c .reg_offset = 0, reg_offset 69 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 73 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 77 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 81 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 85 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 89 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 93 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 97 drivers/mfd/da9052-irq.c .reg_offset = 1, reg_offset 101 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 105 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 109 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 113 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 117 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 121 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 125 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 129 drivers/mfd/da9052-irq.c .reg_offset = 2, reg_offset 133 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 137 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 141 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 145 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 149 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 153 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 157 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 161 drivers/mfd/da9052-irq.c .reg_offset = 3, reg_offset 223 drivers/mfd/da9055-core.c .reg_offset = 0, reg_offset 227 drivers/mfd/da9055-core.c .reg_offset = 0, reg_offset 231 drivers/mfd/da9055-core.c .reg_offset = 0, reg_offset 235 drivers/mfd/da9055-core.c .reg_offset = 0, reg_offset 239 drivers/mfd/da9055-core.c .reg_offset = 1, reg_offset 27 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 31 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 35 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 40 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 44 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 48 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 52 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 57 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 61 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 65 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 69 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 73 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 91 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 95 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 99 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 103 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 107 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_A_OFFSET, reg_offset 112 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 116 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 120 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 124 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_B_OFFSET, reg_offset 129 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 133 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 137 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 141 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 145 drivers/mfd/da9062-core.c .reg_offset = DA9062_REG_EVENT_C_OFFSET, reg_offset 258 drivers/mfd/da9150-core.c .reg_offset = 0, reg_offset 262 drivers/mfd/da9150-core.c .reg_offset = 0, reg_offset 266 drivers/mfd/da9150-core.c .reg_offset = 0, reg_offset 270 drivers/mfd/da9150-core.c .reg_offset = 0, reg_offset 274 drivers/mfd/da9150-core.c .reg_offset = 0, reg_offset 278 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 282 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 286 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 290 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 294 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 298 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 302 drivers/mfd/da9150-core.c .reg_offset = 1, reg_offset 306 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 310 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 314 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 318 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 322 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 326 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 330 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 334 drivers/mfd/da9150-core.c .reg_offset = 2, reg_offset 338 drivers/mfd/da9150-core.c .reg_offset = 3, reg_offset 25 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = OTMP_D1R_INT_MASK }, reg_offset 26 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK }, reg_offset 27 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK }, reg_offset 28 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK }, reg_offset 29 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK }, reg_offset 30 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D20F_INT_MASK }, reg_offset 31 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D20R_INT_MASK }, reg_offset 32 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = RESERVE_INT_MASK }, reg_offset 193 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, }, reg_offset 194 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, }, reg_offset 195 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, }, reg_offset 197 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, }, reg_offset 198 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, }, reg_offset 199 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, }, reg_offset 200 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, }, reg_offset 201 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, }, reg_offset 203 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, }, reg_offset 204 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, }, reg_offset 205 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, }, reg_offset 206 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, }, reg_offset 221 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, }, reg_offset 222 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, }, reg_offset 223 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, }, reg_offset 224 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, }, reg_offset 226 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, }, reg_offset 227 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, }, reg_offset 228 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, }, reg_offset 229 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, }, reg_offset 230 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, }, reg_offset 231 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, }, reg_offset 233 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, }, reg_offset 234 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, }, reg_offset 235 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, }, reg_offset 236 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, }, reg_offset 250 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, }, reg_offset 251 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, }, reg_offset 99 drivers/mfd/max77650.c .reg_offset = MAX77650_INT_GLBL_OFFSET, reg_offset 117 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, }, reg_offset 118 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, }, reg_offset 119 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, }, reg_offset 120 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, }, reg_offset 121 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, }, reg_offset 122 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, }, reg_offset 123 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, }, reg_offset 124 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, }, reg_offset 126 drivers/mfd/max77686.c { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, }, reg_offset 127 drivers/mfd/max77686.c { .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, }, reg_offset 116 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, }, reg_offset 117 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, }, reg_offset 118 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, }, reg_offset 119 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, }, reg_offset 121 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, }, reg_offset 122 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, }, reg_offset 123 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, }, reg_offset 124 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, }, reg_offset 125 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, }, reg_offset 126 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, }, reg_offset 128 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, }, reg_offset 129 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, }, reg_offset 130 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, }, reg_offset 131 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, }, reg_offset 132 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, }, reg_offset 133 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, }, reg_offset 52 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, }, reg_offset 53 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, }, reg_offset 54 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, }, reg_offset 55 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, }, reg_offset 116 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 0, }, reg_offset 117 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 1, }, reg_offset 118 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, reg_offset 119 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 0, }, reg_offset 120 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 1, }, reg_offset 121 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 2, }, reg_offset 122 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 3, }, reg_offset 123 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 4, }, reg_offset 124 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 5, }, reg_offset 125 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 6, }, reg_offset 126 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 7, }, reg_offset 141 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 0, }, reg_offset 142 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 1, }, reg_offset 143 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, reg_offset 144 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 3, }, reg_offset 145 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 4, }, reg_offset 146 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 5, }, reg_offset 147 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 6, }, reg_offset 148 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 7, }, reg_offset 149 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 0, }, reg_offset 150 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 1, }, reg_offset 164 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, reg_offset 165 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 3, }, reg_offset 441 drivers/mfd/mc13xxx-core.c mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG; reg_offset 126 drivers/mfd/motorola-cpcap.c unsigned int reg_offset; reg_offset 129 drivers/mfd/motorola-cpcap.c reg_offset = irq - irq_base; reg_offset 130 drivers/mfd/motorola-cpcap.c reg_offset /= cpcap->regmap_conf->val_bits; reg_offset 131 drivers/mfd/motorola-cpcap.c reg_offset *= cpcap->regmap_conf->reg_stride; reg_offset 136 drivers/mfd/motorola-cpcap.c rirq->reg_offset = reg_offset; reg_offset 73 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 77 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 81 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 85 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 89 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 93 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 97 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 101 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 106 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 110 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 114 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 118 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 122 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 126 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 130 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 134 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 139 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 143 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 147 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 151 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 155 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 159 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 163 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 167 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 200 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 204 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 208 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 212 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 216 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 220 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 224 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 228 drivers/mfd/palmas.c .reg_offset = 1, reg_offset 233 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 237 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 241 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 245 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 249 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 253 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 257 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 261 drivers/mfd/palmas.c .reg_offset = 2, reg_offset 266 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 270 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 274 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 278 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 282 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 286 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 290 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 294 drivers/mfd/palmas.c .reg_offset = 3, reg_offset 350 drivers/mfd/palmas.c reg_add += pmic_ddata->sleep_req_info[id].reg_offset; reg_offset 244 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 248 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 252 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 256 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 260 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 264 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 268 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 272 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 280 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 284 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 288 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 292 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 296 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 300 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 304 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 310 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 314 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 322 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 326 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 330 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 334 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 338 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 342 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 346 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 350 drivers/mfd/rk808.c .reg_offset = 0, reg_offset 356 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 360 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 364 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 368 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 372 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 376 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 380 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 384 drivers/mfd/rk808.c .reg_offset = 1, reg_offset 22 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 26 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 30 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 34 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 38 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 42 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 46 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 50 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 54 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 58 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 62 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 66 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 70 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 74 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 78 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 82 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 89 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 93 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 97 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 101 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 105 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 109 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 113 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 117 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 121 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 125 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 129 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 133 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 137 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 141 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 145 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 149 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 153 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 160 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 164 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 168 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 172 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 176 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 180 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 184 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 188 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 192 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 196 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 200 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 204 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 208 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 212 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 216 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 220 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 224 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 231 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 235 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 239 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 243 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 247 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 251 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 255 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 259 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 263 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 267 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 271 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 275 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 279 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 283 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 287 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 291 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 295 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 302 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 306 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 310 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 314 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 318 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 322 drivers/mfd/sec-irq.c .reg_offset = 0, reg_offset 326 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 330 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 334 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 338 drivers/mfd/sec-irq.c .reg_offset = 1, reg_offset 342 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 346 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 350 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 354 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 358 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 362 drivers/mfd/sec-irq.c .reg_offset = 2, reg_offset 366 drivers/mfd/sec-irq.c .reg_offset = 3, reg_offset 370 drivers/mfd/sec-irq.c .reg_offset = 3, reg_offset 202 drivers/mfd/sprd-sc27xx-spi.c ddata->irqs[i].reg_offset = i / pdata->num_irqs; reg_offset 91 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 95 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 99 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 103 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 107 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 111 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 115 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 119 drivers/mfd/tps65090.c .reg_offset = 1, reg_offset 170 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 174 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 178 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 182 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 186 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 190 drivers/mfd/tps65218.c .reg_offset = 1, reg_offset 54 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 58 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 62 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 66 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 70 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 74 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 78 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 82 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 88 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 92 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 96 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 100 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 104 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 108 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 112 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 116 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 122 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 126 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 130 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 134 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 138 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 142 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 146 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 150 drivers/mfd/tps65910.c .reg_offset = 2, reg_offset 158 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 162 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 166 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 170 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 174 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 178 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 182 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 186 drivers/mfd/tps65910.c .reg_offset = 0, reg_offset 192 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 196 drivers/mfd/tps65910.c .reg_offset = 1, reg_offset 84 drivers/mfd/tps80031.c .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \ reg_offset 618 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_THINT, }, reg_offset 619 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, }, reg_offset 620 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_HOOKINT, }, reg_offset 621 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_HFINT, }, reg_offset 622 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_VIBINT, }, reg_offset 623 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_READYINT, }, reg_offset 124 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, reg_offset 125 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, reg_offset 126 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 127 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 130 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 reg_offset 133 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 reg_offset 136 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 reg_offset 140 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 143 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 146 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 reg_offset 149 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 reg_offset 152 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 155 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 reg_offset 158 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 161 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 reg_offset 164 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 reg_offset 167 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 170 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 173 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 176 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 179 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 182 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 186 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 reg_offset 189 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 reg_offset 192 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 reg_offset 195 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 reg_offset 198 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 reg_offset 201 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 204 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 207 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 reg_offset 210 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 reg_offset 213 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 reg_offset 217 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 220 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 reg_offset 223 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 reg_offset 226 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 229 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 310 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, reg_offset 311 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, reg_offset 312 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 313 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 316 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1 reg_offset 319 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 reg_offset 322 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 reg_offset 325 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 reg_offset 328 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 reg_offset 331 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 reg_offset 334 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 reg_offset 337 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 reg_offset 340 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 reg_offset 343 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 reg_offset 346 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 reg_offset 349 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 reg_offset 353 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 356 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 359 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 reg_offset 362 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 reg_offset 365 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 368 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 reg_offset 371 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 374 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 reg_offset 377 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 reg_offset 380 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 383 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 386 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 389 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 392 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 395 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 399 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 reg_offset 402 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 reg_offset 405 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 reg_offset 408 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 reg_offset 411 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 reg_offset 414 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 417 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 420 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 reg_offset 423 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 reg_offset 426 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 reg_offset 429 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 reg_offset 432 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 reg_offset 435 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 reg_offset 438 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 reg_offset 441 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 reg_offset 444 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 reg_offset 448 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 451 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 454 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 470 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, reg_offset 471 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, reg_offset 472 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 473 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 476 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1 reg_offset 479 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 reg_offset 482 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 reg_offset 485 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 reg_offset 488 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 reg_offset 491 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 reg_offset 494 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 reg_offset 497 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 reg_offset 500 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 reg_offset 503 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 reg_offset 506 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 reg_offset 509 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 reg_offset 513 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 516 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 519 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 reg_offset 522 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 reg_offset 525 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 528 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 reg_offset 531 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 534 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 reg_offset 537 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 reg_offset 540 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 543 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 546 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 549 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 552 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 555 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 559 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 reg_offset 562 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 565 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 568 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 reg_offset 571 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 reg_offset 574 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 reg_offset 577 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 reg_offset 580 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 reg_offset 583 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 reg_offset 586 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 reg_offset 589 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 reg_offset 592 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 reg_offset 595 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 reg_offset 599 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 602 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 reg_offset 605 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 608 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 612 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 reg_offset 615 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 reg_offset 618 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 reg_offset 621 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 reg_offset 624 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1 reg_offset 627 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1 reg_offset 630 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1 reg_offset 633 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1 reg_offset 636 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1 reg_offset 639 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1 reg_offset 642 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1 reg_offset 645 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1 reg_offset 648 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1 reg_offset 651 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 reg_offset 654 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1 reg_offset 657 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 reg_offset 28 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 32 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 36 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 40 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 44 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 48 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 52 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 56 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 60 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 64 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 68 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 72 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 76 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 80 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 84 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 88 drivers/mfd/wm8994-irq.c .reg_offset = 1, reg_offset 60 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, reg_offset 61 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, reg_offset 62 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 63 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 66 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 69 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 72 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 reg_offset 75 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 reg_offset 78 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 81 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 84 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 87 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 90 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 93 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 96 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 99 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 103 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 reg_offset 106 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 reg_offset 109 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 reg_offset 112 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 115 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 118 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 reg_offset 121 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 reg_offset 124 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 reg_offset 128 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 131 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 reg_offset 134 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 reg_offset 137 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 140 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 76 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, reg_offset 77 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, reg_offset 78 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, reg_offset 79 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, reg_offset 82 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 reg_offset 85 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 reg_offset 88 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 reg_offset 91 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 reg_offset 94 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 reg_offset 97 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 reg_offset 100 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 reg_offset 103 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 reg_offset 106 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 reg_offset 109 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 reg_offset 112 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 reg_offset 115 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 reg_offset 118 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 reg_offset 121 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 reg_offset 125 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 reg_offset 128 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 reg_offset 131 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 reg_offset 134 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 reg_offset 137 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 reg_offset 140 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 reg_offset 143 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 reg_offset 146 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 reg_offset 149 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 reg_offset 152 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 reg_offset 156 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 reg_offset 159 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 reg_offset 162 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 reg_offset 3450 drivers/misc/habanalabs/goya/goya.c u16 reg_offset; reg_offset 3452 drivers/misc/habanalabs/goya/goya.c reg_offset = le32_to_cpu(wreg_pkt->ctl) & reg_offset 3456 drivers/misc/habanalabs/goya/goya.c dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset); reg_offset 3460 drivers/misc/habanalabs/goya/goya.c if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) { reg_offset 3462 drivers/misc/habanalabs/goya/goya.c reg_offset); reg_offset 251 drivers/misc/xilinx_sdfec.c u32 reg_offset, u32 bit_num, reg_offset 257 drivers/misc/xilinx_sdfec.c reg_val = xsdfec_regread(xsdfec, reg_offset); reg_offset 210 drivers/mmc/host/omap_hsmmc.c u32 reg_offset; reg_offset 1748 drivers/mmc/host/omap_hsmmc.c .reg_offset = 0x100, reg_offset 1751 drivers/mmc/host/omap_hsmmc.c .reg_offset = 0x100, reg_offset 1835 drivers/mmc/host/omap_hsmmc.c pdata->reg_offset = data->reg_offset; reg_offset 1871 drivers/mmc/host/omap_hsmmc.c host->mapbase = res->start + pdata->reg_offset; reg_offset 1872 drivers/mmc/host/omap_hsmmc.c host->base = base + pdata->reg_offset; reg_offset 126 drivers/net/can/m_can/tcan4x5x.c int reg_offset; reg_offset 260 drivers/net/can/m_can/tcan4x5x.c regmap_read(priv->regmap, priv->reg_offset + reg, &val); reg_offset 279 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, priv->reg_offset + reg, val); reg_offset 442 drivers/net/can/m_can/tcan4x5x.c priv->reg_offset = TCAN4X5X_MCAN_OFFSET; reg_offset 93 drivers/net/ethernet/8390/8390.h u32 *reg_offset; /* Register mapping table */ reg_offset 53 drivers/net/ethernet/8390/ax88796.c #define EI_SHIFT(x) (ei_local->reg_offset[(x)]) reg_offset 888 drivers/net/ethernet/8390/ax88796.c ei_local->reg_offset = ax->plat->reg_offsets; reg_offset 890 drivers/net/ethernet/8390/ax88796.c ei_local->reg_offset = ax->reg_offsets; reg_offset 934 drivers/net/ethernet/8390/ax88796.c ei_local->reg_offset[0x1f] = ax->map2 - ei_local->mem; reg_offset 49 drivers/net/ethernet/8390/etherh.c #define EI_SHIFT(x) (ei_local->reg_offset[x]) reg_offset 728 drivers/net/ethernet/8390/etherh.c ei_local->reg_offset = etherm_regoffsets; reg_offset 731 drivers/net/ethernet/8390/etherh.c ei_local->reg_offset = etherh_regoffsets; reg_offset 33 drivers/net/ethernet/8390/hydra.c #define EI_SHIFT(x) (ei_local->reg_offset[x]) reg_offset 161 drivers/net/ethernet/8390/hydra.c ei_status.reg_offset = hydra_offsets; reg_offset 47 drivers/net/ethernet/8390/mac8390.c #define EI_SHIFT(x) (ei_local->reg_offset[x]) reg_offset 548 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = back4_offsets; reg_offset 557 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = back4_offsets; reg_offset 572 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = back4_offsets; reg_offset 581 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = fwrd2_offsets; reg_offset 592 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = fwrd4_offsets; reg_offset 601 drivers/net/ethernet/8390/mac8390.c ei_status.reg_offset = fwrd4_offsets; reg_offset 391 drivers/net/ethernet/8390/mcf8390.c ei_local->reg_offset = offsets; reg_offset 40 drivers/net/ethernet/8390/xsurf100.c #define EI_SHIFT(x) (ei_local->reg_offset[(x)]) reg_offset 38 drivers/net/ethernet/8390/zorro8390.c #define EI_SHIFT(x) (ei_local->reg_offset[x]) reg_offset 383 drivers/net/ethernet/8390/zorro8390.c ei_status.reg_offset = zorro8390_offsets; reg_offset 90 drivers/net/ethernet/apple/bmac.c unsigned short reg_offset; reg_offset 210 drivers/net/ethernet/apple/bmac.c void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) reg_offset 212 drivers/net/ethernet/apple/bmac.c out_le16((void __iomem *)dev->base_addr + reg_offset, data); reg_offset 217 drivers/net/ethernet/apple/bmac.c unsigned short bmread(struct net_device *dev, unsigned long reg_offset ) reg_offset 219 drivers/net/ethernet/apple/bmac.c return in_le16((void __iomem *)dev->base_addr + reg_offset); reg_offset 1575 drivers/net/ethernet/apple/bmac.c bmread(bmac_devs, reg_entries[i].reg_offset)); reg_offset 409 drivers/net/ethernet/broadcom/bcmsysport.c val = rxchk_readl(priv, s->reg_offset); reg_offset 411 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, 0, s->reg_offset); reg_offset 414 drivers/net/ethernet/broadcom/bcmsysport.c val = rbuf_readl(priv, s->reg_offset); reg_offset 416 drivers/net/ethernet/broadcom/bcmsysport.c rbuf_writel(priv, 0, s->reg_offset); reg_offset 650 drivers/net/ethernet/broadcom/bcmsysport.h .reg_offset = ofs, \ reg_offset 658 drivers/net/ethernet/broadcom/bcmsysport.h .reg_offset = ofs, \ reg_offset 670 drivers/net/ethernet/broadcom/bcmsysport.h u16 reg_offset; reg_offset 4144 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int reg_offset; reg_offset 4147 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : reg_offset 4152 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); reg_offset 4154 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); reg_offset 4171 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); reg_offset 4173 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); reg_offset 4197 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int reg_offset; reg_offset 4199 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : reg_offset 4202 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); reg_offset 4204 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); reg_offset 4241 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int reg_offset; reg_offset 4243 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : reg_offset 4246 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = REG_RD(bp, reg_offset); reg_offset 4248 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, val); reg_offset 6023 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int reg_offset, reg_offset_en5; reg_offset 6044 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : reg_offset 6053 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); reg_offset 6068 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : reg_offset 6071 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset, U64_LO(section)); reg_offset 6072 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg_offset + 4, U64_HI(section)); reg_offset 804 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : reg_offset 818 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c reg_offset += 8*index; reg_offset 824 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c REG_WR_DMAE(bp, reg_offset, wb_data, 2); reg_offset 723 drivers/net/ethernet/broadcom/genet/bcmgenet.c u16 reg_offset; reg_offset 750 drivers/net/ethernet/broadcom/genet/bcmgenet.c .reg_offset = offset, \ reg_offset 970 drivers/net/ethernet/broadcom/genet/bcmgenet.c val = bcmgenet_umac_readl(priv, s->reg_offset); reg_offset 974 drivers/net/ethernet/broadcom/genet/bcmgenet.c s->reg_offset); reg_offset 977 drivers/net/ethernet/broadcom/genet/bcmgenet.c s->reg_offset); reg_offset 74 drivers/net/ethernet/brocade/bna/bna_hw_defs.h struct bna_reg_offset reg_offset[] = \ reg_offset 81 drivers/net/ethernet/brocade/bna/bna_hw_defs.h reg_offset[(_pcidev)->pci_func].fn_int_status;\ reg_offset 83 drivers/net/ethernet/brocade/bna/bna_hw_defs.h reg_offset[(_pcidev)->pci_func].fn_int_mask;\ reg_offset 1561 drivers/net/ethernet/calxeda/xgmac.c #define XGMAC_HW_STAT(m, reg_offset) \ reg_offset 1562 drivers/net/ethernet/calxeda/xgmac.c { #m, reg_offset, true } reg_offset 369 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c u64 reg_offset; reg_offset 421 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c reg_offset = NIC_QSET_RQ_0_7_STAT_0_1 | (1 << 3); reg_offset 422 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); reg_offset 439 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c reg_offset = NIC_QSET_SQ_0_7_STAT_0_1 | (1 << 3); reg_offset 440 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); reg_offset 454 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c reg_offset = NIC_QSET_RBDR_0_1_PREFETCH_STATUS; reg_offset 455 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); reg_offset 61 drivers/net/ethernet/chelsio/cxgb/espi.c int ch_addr, int reg_offset, u32 wr_data) reg_offset 66 drivers/net/ethernet/chelsio/cxgb/espi.c V_REGISTER_OFFSET(reg_offset) | reg_offset 630 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0); reg_offset 661 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c ret = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset, reg_offset 667 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin); reg_offset 671 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en); reg_offset 2072 drivers/net/ethernet/intel/igb/e1000_82575.c u32 reg_val, reg_offset; reg_offset 2076 drivers/net/ethernet/intel/igb/e1000_82575.c reg_offset = E1000_DTXSWC; reg_offset 2080 drivers/net/ethernet/intel/igb/e1000_82575.c reg_offset = E1000_TXSWC; reg_offset 2086 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val = rd32(reg_offset); reg_offset 2098 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(reg_offset, reg_val); reg_offset 988 drivers/net/ethernet/intel/igb/igb_ethtool.c u16 reg_offset; reg_offset 1315 drivers/net/ethernet/intel/igb/igb_ethtool.c (i * test->reg_offset), reg_offset 1321 drivers/net/ethernet/intel/igb/igb_ethtool.c (i * test->reg_offset), reg_offset 1328 drivers/net/ethernet/intel/igb/igb_ethtool.c + (i * test->reg_offset)); reg_offset 9285 drivers/net/ethernet/intel/igb/igb_main.c u32 reg_val, reg_offset; reg_offset 9293 drivers/net/ethernet/intel/igb/igb_main.c reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; reg_offset 9294 drivers/net/ethernet/intel/igb/igb_main.c reg_val = rd32(reg_offset); reg_offset 9301 drivers/net/ethernet/intel/igb/igb_main.c wr32(reg_offset, reg_val); reg_offset 1280 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u16 reg_offset; reg_offset 1287 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); reg_offset 1291 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); reg_offset 1308 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, reg_offset, txctrl); reg_offset 4195 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 reg_offset, vf_shift, vmolr; reg_offset 4217 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; reg_offset 4220 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); reg_offset 4221 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); reg_offset 4222 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); reg_offset 4223 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); reg_offset 4603 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); reg_offset 4604 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); reg_offset 4607 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, reg_offset, vlvfb); reg_offset 274 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c u32 reg_offset = (vf_number < 32) ? 0 : 1; reg_offset 280 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); reg_offset 286 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); reg_offset 293 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), BIT(vf_shift)); reg_offset 486 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 reg_offset, vf_shift, vfre; reg_offset 520 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg_offset = vf / 32; reg_offset 523 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); reg_offset 528 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre); reg_offset 830 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 reg, reg_offset, vf_shift; reg_offset 848 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg_offset = vf / 32; reg_offset 851 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); reg_offset 853 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); reg_offset 863 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); reg_offset 882 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); reg_offset 888 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); reg_offset 890 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); reg_offset 1533 drivers/net/ethernet/marvell/mvneta.c unsigned int reg_offset; reg_offset 1542 drivers/net/ethernet/marvell/mvneta.c reg_offset = last_nibble % 4; reg_offset 1548 drivers/net/ethernet/marvell/mvneta.c unicast_reg &= ~(0xff << (8 * reg_offset)); reg_offset 1550 drivers/net/ethernet/marvell/mvneta.c unicast_reg &= ~(0xff << (8 * reg_offset)); reg_offset 1551 drivers/net/ethernet/marvell/mvneta.c unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); reg_offset 2578 drivers/net/ethernet/marvell/mvneta.c unsigned int reg_offset; reg_offset 2583 drivers/net/ethernet/marvell/mvneta.c reg_offset = last_byte % 4; reg_offset 2589 drivers/net/ethernet/marvell/mvneta.c smc_table_reg &= ~(0xff << (8 * reg_offset)); reg_offset 2591 drivers/net/ethernet/marvell/mvneta.c smc_table_reg &= ~(0xff << (8 * reg_offset)); reg_offset 2592 drivers/net/ethernet/marvell/mvneta.c smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); reg_offset 2613 drivers/net/ethernet/marvell/mvneta.c unsigned int reg_offset; reg_offset 2616 drivers/net/ethernet/marvell/mvneta.c reg_offset = crc8 % 4; /* Entry offset within the above reg */ reg_offset 2622 drivers/net/ethernet/marvell/mvneta.c omc_table_reg &= ~(0xff << (8 * reg_offset)); reg_offset 2624 drivers/net/ethernet/marvell/mvneta.c omc_table_reg &= ~(0xff << (8 * reg_offset)); reg_offset 2625 drivers/net/ethernet/marvell/mvneta.c omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); reg_offset 672 drivers/net/ethernet/mediatek/mtk_eth_soc.c base += hw_stats->reg_offset; reg_offset 2827 drivers/net/ethernet/mediatek/mtk_eth_soc.c mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; reg_offset 519 drivers/net/ethernet/mediatek/mtk_eth_soc.h u32 reg_offset; reg_offset 69 drivers/net/ethernet/natsemi/macsonic.c + lp->reg_offset)) reg_offset 71 drivers/net/ethernet/natsemi/macsonic.c + lp->reg_offset)) reg_offset 329 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset = 0; reg_offset 337 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset = 2; reg_offset 346 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset = 0; reg_offset 350 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset = 2; reg_offset 356 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset); reg_offset 434 drivers/net/ethernet/natsemi/macsonic.c int reg_offset, dma_bitmode; reg_offset 442 drivers/net/ethernet/natsemi/macsonic.c reg_offset = 2; reg_offset 449 drivers/net/ethernet/natsemi/macsonic.c reg_offset = 0; reg_offset 457 drivers/net/ethernet/natsemi/macsonic.c reg_offset = 0; reg_offset 465 drivers/net/ethernet/natsemi/macsonic.c reg_offset = 0; reg_offset 473 drivers/net/ethernet/natsemi/macsonic.c reg_offset = 0; reg_offset 484 drivers/net/ethernet/natsemi/macsonic.c lp->reg_offset = reg_offset; reg_offset 490 drivers/net/ethernet/natsemi/macsonic.c lp->dma_bitmode ? 32 : 16, lp->reg_offset); reg_offset 300 drivers/net/ethernet/natsemi/sonic.h int reg_offset; reg_offset 2255 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; reg_offset 2343 drivers/net/ethernet/qlogic/qed/qed_cxt.c reg_offset = PSWRQ2_REG_ILT_MEMORY + reg_offset 2354 drivers/net/ethernet/qlogic/qed/qed_cxt.c reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), reg_offset 2389 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 reg_offset, elem_size, hw_p_size, elems_per_p; reg_offset 2450 drivers/net/ethernet/qlogic/qed/qed_cxt.c reg_offset = PSWRQ2_REG_ILT_MEMORY + reg_offset 2459 drivers/net/ethernet/qlogic/qed/qed_cxt.c reg_offset, reg_offset 2638 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 offset = 0, reg_offset = 0; reg_offset 2645 drivers/net/ethernet/qlogic/qed/qed_debug.c while (reg_offset < total_len) { reg_offset 2646 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 curr_len = min_t(u32, read_len, total_len - reg_offset); reg_offset 2653 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_offset += curr_len; reg_offset 2656 drivers/net/ethernet/qlogic/qed/qed_debug.c if (reg_offset < total_len) { reg_offset 2660 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_offset += curr_len; reg_offset 4185 drivers/net/ethernet/qlogic/qed/qed_debug.c s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; reg_offset 4325 drivers/net/ethernet/qlogic/qed/qed_debug.c [rule->reg_offset]; reg_offset 2172 drivers/net/ethernet/qlogic/qed/qed_hsi.h u16 reg_offset; /* offset of this rules registers in the idle check reg_offset 405 drivers/net/ethernet/renesas/sh_eth.c u16 offset = mdp->reg_offset[enum_index]; reg_offset 416 drivers/net/ethernet/renesas/sh_eth.c u16 offset = mdp->reg_offset[enum_index]; reg_offset 433 drivers/net/ethernet/renesas/sh_eth.c return mdp->reg_offset[enum_index]; reg_offset 2125 drivers/net/ethernet/renesas/sh_eth.c if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ reg_offset 2242 drivers/net/ethernet/renesas/sh_eth.c mdp->reg_offset[TSU_ADRH0] + reg_offset 2769 drivers/net/ethernet/renesas/sh_eth.c u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); reg_offset 2773 drivers/net/ethernet/renesas/sh_eth.c for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { reg_offset 2774 drivers/net/ethernet/renesas/sh_eth.c sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); reg_offset 2796 drivers/net/ethernet/renesas/sh_eth.c u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); reg_offset 2804 drivers/net/ethernet/renesas/sh_eth.c ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); reg_offset 2813 drivers/net/ethernet/renesas/sh_eth.c u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); reg_offset 2825 drivers/net/ethernet/renesas/sh_eth.c ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); reg_offset 2887 drivers/net/ethernet/renesas/sh_eth.c u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); reg_offset 2894 drivers/net/ethernet/renesas/sh_eth.c for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { reg_offset 2895 drivers/net/ethernet/renesas/sh_eth.c sh_eth_tsu_read_entry(ndev, reg_offset, addr); reg_offset 3100 drivers/net/ethernet/renesas/sh_eth.c bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; reg_offset 3132 drivers/net/ethernet/renesas/sh_eth.c const u16 *reg_offset = NULL; reg_offset 3136 drivers/net/ethernet/renesas/sh_eth.c reg_offset = sh_eth_offset_gigabit; reg_offset 3139 drivers/net/ethernet/renesas/sh_eth.c reg_offset = sh_eth_offset_fast_rz; reg_offset 3142 drivers/net/ethernet/renesas/sh_eth.c reg_offset = sh_eth_offset_fast_rcar; reg_offset 3145 drivers/net/ethernet/renesas/sh_eth.c reg_offset = sh_eth_offset_fast_sh4; reg_offset 3148 drivers/net/ethernet/renesas/sh_eth.c reg_offset = sh_eth_offset_fast_sh3_sh2; reg_offset 3152 drivers/net/ethernet/renesas/sh_eth.c return reg_offset; reg_offset 3299 drivers/net/ethernet/renesas/sh_eth.c mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); reg_offset 3300 drivers/net/ethernet/renesas/sh_eth.c if (!mdp->reg_offset) { reg_offset 516 drivers/net/ethernet/renesas/sh_eth.h const u16 *reg_offset; reg_offset 443 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c int reg_offset; reg_offset 450 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c for (reg_offset = START_MAC_REG_OFFSET; reg_offset 451 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_offset <= MAX_MAC_REG_OFFSET; reg_offset += 4) { reg_offset 452 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_space[reg_ix] = readl(ioaddr + reg_offset); reg_offset 457 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c for (reg_offset = START_MTL_REG_OFFSET; reg_offset 458 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) { reg_offset 459 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_space[reg_ix] = readl(ioaddr + reg_offset); reg_offset 464 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c for (reg_offset = START_DMA_REG_OFFSET; reg_offset 465 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) { reg_offset 466 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_space[reg_ix] = readl(ioaddr + reg_offset); reg_offset 49 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 reg_offset; reg_offset 104 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 reg_offset, reg_shift; reg_offset 119 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); reg_offset 218 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c dwmac->reg_offset = reg_offset; reg_offset 266 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 reg_offset = dwmac->reg_offset; reg_offset 286 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); reg_offset 307 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c regmap_write(sys_mgr_base_addr, reg_offset, ctrl); reg_offset 328 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c u32 reg_offset = dwmac->reg_offset; reg_offset 346 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); reg_offset 364 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c regmap_write(sys_mgr_base_addr, reg_offset, ctrl); reg_offset 126 drivers/net/wireless/ath/ath.h unsigned int (*read)(void *, u32 reg_offset); reg_offset 128 drivers/net/wireless/ath/ath.h void (*write)(void *, u32 val, u32 reg_offset); reg_offset 131 drivers/net/wireless/ath/ath.h u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); reg_offset 68 drivers/net/wireless/ath/ath10k/qmi.h __le16 reg_offset; reg_offset 69 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), reg_offset 74 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), reg_offset 79 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), reg_offset 84 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), reg_offset 89 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), reg_offset 94 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 99 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 104 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 109 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 114 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 119 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 124 drivers/net/wireless/ath/ath10k/snoc.c .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), reg_offset 232 drivers/net/wireless/ath/ath5k/base.c static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) reg_offset 235 drivers/net/wireless/ath/ath5k/base.c return ath5k_hw_reg_read(ah, reg_offset); reg_offset 238 drivers/net/wireless/ath/ath5k/base.c static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) reg_offset 241 drivers/net/wireless/ath/ath5k/base.c ath5k_hw_reg_write(ah, val, reg_offset); reg_offset 234 drivers/net/wireless/ath/ath9k/htc_drv_init.c static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) reg_offset 239 drivers/net/wireless/ath/ath9k/htc_drv_init.c __be32 val, reg = cpu_to_be32(reg_offset); reg_offset 248 drivers/net/wireless/ath/ath9k/htc_drv_init.c reg_offset, r); reg_offset 302 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) reg_offset 308 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(reg_offset), reg_offset 319 drivers/net/wireless/ath/ath9k/htc_drv_init.c reg_offset, r); reg_offset 323 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) reg_offset 333 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(reg_offset); reg_offset 346 drivers/net/wireless/ath/ath9k/htc_drv_init.c static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) reg_offset 353 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_regwrite_buffer(hw_priv, val, reg_offset); reg_offset 355 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_regwrite_single(hw_priv, val, reg_offset); reg_offset 384 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 reg_offset, u32 set, u32 clr) reg_offset 396 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(reg_offset); reg_offset 467 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 reg_offset, u32 set, u32 clr) reg_offset 475 drivers/net/wireless/ath/ath9k/htc_drv_init.c buf.reg = cpu_to_be32(reg_offset); reg_offset 485 drivers/net/wireless/ath/ath9k/htc_drv_init.c reg_offset, ret); reg_offset 489 drivers/net/wireless/ath/ath9k/htc_drv_init.c static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) reg_offset 498 drivers/net/wireless/ath/ath9k/htc_drv_init.c val = REG_READ(ah, reg_offset); reg_offset 501 drivers/net/wireless/ath/ath9k/htc_drv_init.c REG_WRITE(ah, reg_offset, val); reg_offset 507 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr); reg_offset 509 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr); reg_offset 173 drivers/net/wireless/ath/ath9k/init.c static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) reg_offset 182 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); reg_offset 185 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); reg_offset 188 drivers/net/wireless/ath/ath9k/init.c static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) reg_offset 198 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); reg_offset 201 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); reg_offset 215 drivers/net/wireless/ath/ath9k/init.c static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, reg_offset 220 drivers/net/wireless/ath/ath9k/init.c val = ioread32(sc->mem + reg_offset); reg_offset 223 drivers/net/wireless/ath/ath9k/init.c iowrite32(val, sc->mem + reg_offset); reg_offset 228 drivers/net/wireless/ath/ath9k/init.c static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) reg_offset 238 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); reg_offset 241 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); reg_offset 344 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) reg_offset 346 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c void __iomem *address = devinfo->regs + reg_offset; reg_offset 353 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, reg_offset 356 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c void __iomem *address = devinfo->regs + reg_offset; reg_offset 2567 drivers/net/wireless/intel/iwlegacy/3945.c u32 reg_offset; reg_offset 2591 drivers/net/wireless/intel/iwlegacy/3945.c for (reg_offset = BSM_SRAM_LOWER_BOUND; reg_offset 2592 drivers/net/wireless/intel/iwlegacy/3945.c reg_offset < BSM_SRAM_LOWER_BOUND + len; reg_offset 2593 drivers/net/wireless/intel/iwlegacy/3945.c reg_offset += sizeof(u32), image++) reg_offset 2594 drivers/net/wireless/intel/iwlegacy/3945.c _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); reg_offset 337 drivers/net/wireless/intel/iwlegacy/4965.c u32 reg_offset; reg_offset 365 drivers/net/wireless/intel/iwlegacy/4965.c for (reg_offset = BSM_SRAM_LOWER_BOUND; reg_offset 366 drivers/net/wireless/intel/iwlegacy/4965.c reg_offset < BSM_SRAM_LOWER_BOUND + len; reg_offset 367 drivers/net/wireless/intel/iwlegacy/4965.c reg_offset += sizeof(u32), image++) reg_offset 368 drivers/net/wireless/intel/iwlegacy/4965.c _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); reg_offset 429 drivers/net/wireless/marvell/mwifiex/debugfs.c u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX; reg_offset 435 drivers/net/wireless/marvell/mwifiex/debugfs.c sscanf(buf, "%u %x %x", ®_type, ®_offset, ®_value); reg_offset 437 drivers/net/wireless/marvell/mwifiex/debugfs.c if (reg_type == 0 || reg_offset == 0) { reg_offset 442 drivers/net/wireless/marvell/mwifiex/debugfs.c saved_reg_offset = reg_offset; reg_offset 1523 drivers/net/wireless/marvell/mwifiex/main.h u32 reg_offset, u32 reg_value); reg_offset 1526 drivers/net/wireless/marvell/mwifiex/main.h u32 reg_offset, u32 *value); reg_offset 1256 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c u32 reg_offset, u32 reg_value) reg_offset 1261 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c reg_rw.offset = reg_offset; reg_offset 1275 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c u32 reg_offset, u32 *value) reg_offset 1281 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c reg_rw.offset = reg_offset; reg_offset 41 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | reg_offset 55 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); reg_offset 56 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); reg_offset 156 drivers/pci/controller/dwc/pci-keystone.c u32 reg_offset; reg_offset 162 drivers/pci/controller/dwc/pci-keystone.c reg_offset = irq % 8; reg_offset 165 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), reg_offset 167 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); reg_offset 202 drivers/pci/controller/dwc/pci-keystone.c u32 reg_offset; reg_offset 210 drivers/pci/controller/dwc/pci-keystone.c reg_offset = irq % 8; reg_offset 213 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), reg_offset 226 drivers/pci/controller/dwc/pci-keystone.c u32 reg_offset; reg_offset 234 drivers/pci/controller/dwc/pci-keystone.c reg_offset = irq % 8; reg_offset 237 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), reg_offset 405 drivers/pci/controller/pcie-iproc.c static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) reg_offset 407 drivers/pci/controller/pcie-iproc.c return !!(reg_offset == IPROC_PCIE_REG_INVALID); reg_offset 422 drivers/pci/pci-acpi.c u16 reg_offset; reg_offset 542 drivers/pci/pci-acpi.c pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); reg_offset 550 drivers/pci/pci-acpi.c pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); reg_offset 581 drivers/pci/pci-acpi.c hpx3_reg->reg_offset = reg_fields[11].integer.value; reg_offset 416 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg_offset, u32 field) reg_offset 422 drivers/phy/broadcom/phy-brcm-usb-init.c reg = params->ctrl_regs + reg_offset; reg_offset 428 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg_offset, u32 field) reg_offset 434 drivers/phy/broadcom/phy-brcm-usb-init.c reg = params->ctrl_regs + reg_offset; reg_offset 22 drivers/phy/qualcomm/phy-qcom-ufs-i.h .reg_offset = reg, \ reg_offset 44 drivers/phy/qualcomm/phy-qcom-ufs-i.h u32 reg_offset; reg_offset 33 drivers/phy/qualcomm/phy-qcom-ufs.c ufs_qcom_phy->mmio + tbl_A[i].reg_offset); reg_offset 51 drivers/phy/qualcomm/phy-qcom-ufs.c ufs_qcom_phy->mmio + tbl_B[i].reg_offset); reg_offset 79 drivers/phy/rockchip/phy-rockchip-emmc.c unsigned int reg_offset; reg_offset 99 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON6, reg_offset 104 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON6, reg_offset 157 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON6, reg_offset 170 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_STATUS, reg_offset 180 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON0, reg_offset 186 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON6, reg_offset 218 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_STATUS, reg_offset 279 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON6, reg_offset 286 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON0, reg_offset 293 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset + GRF_EMMCPHY_CON0, reg_offset 337 drivers/phy/rockchip/phy-rockchip-emmc.c unsigned int reg_offset; reg_offset 353 drivers/phy/rockchip/phy-rockchip-emmc.c if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { reg_offset 359 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_offset = reg_offset; reg_offset 70 drivers/phy/rockchip/phy-rockchip-usb.c unsigned int reg_offset; reg_offset 85 drivers/phy/rockchip/phy-rockchip-usb.c return regmap_write(phy->base->reg_base, phy->reg_offset, val); reg_offset 125 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); reg_offset 206 drivers/phy/rockchip/phy-rockchip-usb.c unsigned int reg_offset; reg_offset 218 drivers/phy/rockchip/phy-rockchip-usb.c if (of_property_read_u32(child, "reg", ®_offset)) { reg_offset 228 drivers/phy/rockchip/phy-rockchip-usb.c rk_phy->reg_offset = reg_offset; reg_offset 237 drivers/phy/rockchip/phy-rockchip-usb.c if (base->pdata->phys[i].reg == reg_offset) { reg_offset 86 drivers/pinctrl/freescale/pinctrl-imx1-core.c u32 value, u32 reg_offset) reg_offset 88 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg_offset 113 drivers/pinctrl/freescale/pinctrl-imx1-core.c u32 value, u32 reg_offset) reg_offset 115 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg_offset 133 drivers/pinctrl/freescale/pinctrl-imx1-core.c u32 reg_offset) reg_offset 135 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg_offset 146 drivers/pinctrl/freescale/pinctrl-imx1-core.c u32 reg_offset) reg_offset 148 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg_offset 572 drivers/pinctrl/intel/pinctrl-baytrail.c u32 reg_offset; reg_offset 580 drivers/pinctrl/intel/pinctrl-baytrail.c reg_offset = (offset / 32) * 4; reg_offset 583 drivers/pinctrl/intel/pinctrl-baytrail.c reg_offset = 0; reg_offset 586 drivers/pinctrl/intel/pinctrl-baytrail.c reg_offset = comm->pad_map[offset] * 16; reg_offset 590 drivers/pinctrl/intel/pinctrl-baytrail.c return comm->pad_regs + reg_offset + reg; reg_offset 87 drivers/pinctrl/mediatek/mtk-eint.c unsigned int reg_offset; reg_offset 97 drivers/pinctrl/mediatek/mtk-eint.c reg_offset = eint->regs->pol_clr; reg_offset 99 drivers/pinctrl/mediatek/mtk-eint.c reg_offset = eint->regs->pol_set; reg_offset 100 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg + reg_offset); reg_offset 985 drivers/pinctrl/pinctrl-lpc18xx.c u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0; reg_offset 997 drivers/pinctrl/pinctrl-lpc18xx.c reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32); reg_offset 999 drivers/pinctrl/pinctrl-lpc18xx.c reg_val = readl(scu->base + reg_offset); reg_offset 1002 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg_val, scu->base + reg_offset); reg_offset 1089 drivers/pinctrl/pinctrl-st.c int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; reg_offset 1096 drivers/pinctrl/pinctrl-st.c struct reg_field reg = REG_FIELD(reg_offset, 0, 31); reg_offset 1100 drivers/pinctrl/pinctrl-st.c reg_offset += 4; reg_offset 27 drivers/pinctrl/samsung/pinctrl-exynos-arm.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, reg_offset 32 drivers/pinctrl/samsung/pinctrl-exynos-arm.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, reg_offset 24 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, reg_offset 29 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, reg_offset 35 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, reg_offset 40 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, reg_offset 166 drivers/pinctrl/samsung/pinctrl-exynos.c reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; reg_offset 189 drivers/pinctrl/samsung/pinctrl-exynos.c reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; reg_offset 44 drivers/pinctrl/samsung/pinctrl-s3c24xx.c .reg_offset = { 0x00, 0x04, }, reg_offset 49 drivers/pinctrl/samsung/pinctrl-s3c24xx.c .reg_offset = { 0x00, 0x04, 0x08, }, reg_offset 68 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, reg_offset 73 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x04, 0x08, }, reg_offset 78 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, }, reg_offset 83 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x08, 0x0c, }, reg_offset 88 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, reg_offset 93 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .reg_offset = { 0x00, 0x04, 0x08, }, reg_offset 405 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); reg_offset 408 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); reg_offset 452 drivers/pinctrl/samsung/pinctrl-samsung.c cfg_reg = type->reg_offset[cfg_type]; reg_offset 551 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); reg_offset 555 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); reg_offset 579 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); reg_offset 603 drivers/pinctrl/samsung/pinctrl-samsung.c + type->reg_offset[PINCFG_TYPE_FUNC]; reg_offset 1156 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *offs = bank->type->reg_offset; reg_offset 1209 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *offs = bank->type->reg_offset; reg_offset 104 drivers/pinctrl/samsung/pinctrl-samsung.h u8 reg_offset[PINCFG_TYPE_NUM]; reg_offset 373 drivers/platform/x86/intel_pmc_core.c static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) reg_offset 375 drivers/platform/x86/intel_pmc_core.c return readl(pmcdev->regbase + reg_offset); reg_offset 379 drivers/platform/x86/intel_pmc_core.c reg_offset, u32 val) reg_offset 381 drivers/platform/x86/intel_pmc_core.c writel(val, pmcdev->regbase + reg_offset); reg_offset 203 drivers/platform/x86/pmc_atom.c static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) reg_offset 205 drivers/platform/x86/pmc_atom.c return readl(pmc->regmap + reg_offset); reg_offset 208 drivers/platform/x86/pmc_atom.c static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) reg_offset 210 drivers/platform/x86/pmc_atom.c writel(val, pmc->regmap + reg_offset); reg_offset 394 drivers/power/supply/sbs-battery.c int reg_offset, enum power_supply_property psp, reg_offset 400 drivers/power/supply/sbs-battery.c ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); reg_offset 405 drivers/power/supply/sbs-battery.c if (sbs_data[reg_offset].min_value < 0) reg_offset 408 drivers/power/supply/sbs-battery.c if (ret >= sbs_data[reg_offset].min_value && reg_offset 409 drivers/power/supply/sbs-battery.c ret <= sbs_data[reg_offset].max_value) { reg_offset 461 drivers/power/supply/sbs-battery.c int reg_offset, enum power_supply_property psp, char *val) reg_offset 465 drivers/power/supply/sbs-battery.c ret = sbs_read_string_data(client, sbs_data[reg_offset].addr, val); reg_offset 548 drivers/power/supply/sbs-battery.c int reg_offset, enum power_supply_property psp, reg_offset 561 drivers/power/supply/sbs-battery.c ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); reg_offset 66 drivers/pwm/pwm-meson.c u8 reg_offset; reg_offset 73 drivers/pwm/pwm-meson.c .reg_offset = REG_PWM_A, reg_offset 80 drivers/pwm/pwm-meson.c .reg_offset = REG_PWM_B, reg_offset 244 drivers/pwm/pwm-meson.c writel(value, meson->base + channel_data->reg_offset); reg_offset 352 drivers/pwm/pwm-meson.c value = readl(meson->base + channel_data->reg_offset); reg_offset 323 drivers/regulator/palmas-regulator.c .reg_offset = _offset, \ reg_offset 359 drivers/regulator/palmas-regulator.c .reg_offset = _offset, \ reg_offset 99 drivers/reset/reset-simple.c u32 reg_offset; reg_offset 108 drivers/reset/reset-simple.c .reg_offset = 0x20, reg_offset 143 drivers/reset/reset-simple.c u32 reg_offset = 0; reg_offset 164 drivers/reset/reset-simple.c reg_offset = devdata->reg_offset; reg_offset 171 drivers/reset/reset-simple.c data->membase += reg_offset; reg_offset 29 drivers/reset/reset-socfpga.c u32 reg_offset = 0x10; reg_offset 51 drivers/reset/reset-socfpga.c if (of_property_read_u32(np, "altr,modrst-offset", ®_offset)) reg_offset 53 drivers/reset/reset-socfpga.c data->membase += reg_offset; reg_offset 4954 drivers/scsi/FlashPoint.c u32 reg_offset; reg_offset 4965 drivers/scsi/FlashPoint.c reg_offset = hp_aramBase; reg_offset 4990 drivers/scsi/FlashPoint.c WR_HARP32(p_port, reg_offset, addr); reg_offset 4991 drivers/scsi/FlashPoint.c reg_offset += 4; reg_offset 4993 drivers/scsi/FlashPoint.c WR_HARP32(p_port, reg_offset, count); reg_offset 4994 drivers/scsi/FlashPoint.c reg_offset += 4; reg_offset 55 drivers/soc/qcom/spm.c const u8 *reg_offset; reg_offset 78 drivers/soc/qcom/spm.c .reg_offset = spm_reg_offset_v2_1, reg_offset 99 drivers/soc/qcom/spm.c .reg_offset = spm_reg_offset_v1_1, reg_offset 118 drivers/soc/qcom/spm.c if (drv->reg_data->reg_offset[reg]) reg_offset 120 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg_offset 129 drivers/soc/qcom/spm.c if (!drv->reg_data->reg_offset[reg]) reg_offset 134 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg_offset 136 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg_offset 146 drivers/soc/qcom/spm.c return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); reg_offset 344 drivers/soc/qcom/spm.c addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; reg_offset 40 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 49 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 58 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 67 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 76 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 85 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 94 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 103 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 112 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 121 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 130 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 139 drivers/soc/zte/zx296718_pm_domains.c .reg_offset = zx296718_offsets, reg_offset 15 drivers/soc/zte/zx2967_pm_domains.c #define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN]) reg_offset 16 drivers/soc/zte/zx2967_pm_domains.c #define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN]) reg_offset 17 drivers/soc/zte/zx2967_pm_domains.c #define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN]) reg_offset 18 drivers/soc/zte/zx2967_pm_domains.c #define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN]) reg_offset 19 drivers/soc/zte/zx2967_pm_domains.c #define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC]) reg_offset 37 drivers/soc/zte/zx2967_pm_domains.h const u16 *reg_offset; reg_offset 643 drivers/spi/spi-bcm-qspi.c u32 reg_offset = MSPI_RXRAM; reg_offset 644 drivers/spi/spi-bcm-qspi.c u32 lsb_offset = reg_offset + (slot << 3) + 0x4; reg_offset 645 drivers/spi/spi-bcm-qspi.c u32 msb_offset = reg_offset + (slot << 3); reg_offset 694 drivers/spi/spi-bcm-qspi.c u32 reg_offset = MSPI_TXRAM + (slot << 3); reg_offset 697 drivers/spi/spi-bcm-qspi.c bcm_qspi_write(qspi, MSPI, reg_offset, val); reg_offset 703 drivers/spi/spi-bcm-qspi.c u32 reg_offset = MSPI_TXRAM; reg_offset 704 drivers/spi/spi-bcm-qspi.c u32 msb_offset = reg_offset + (slot << 3); reg_offset 705 drivers/spi/spi-bcm-qspi.c u32 lsb_offset = reg_offset + (slot << 3) + 0x4; reg_offset 126 drivers/staging/comedi/drivers/comedi_8254.c unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; reg_offset 133 drivers/staging/comedi/drivers/comedi_8254.c val = readb(i8254->mmio + reg_offset); reg_offset 135 drivers/staging/comedi/drivers/comedi_8254.c val = inb(i8254->iobase + reg_offset); reg_offset 139 drivers/staging/comedi/drivers/comedi_8254.c val = readw(i8254->mmio + reg_offset); reg_offset 141 drivers/staging/comedi/drivers/comedi_8254.c val = inw(i8254->iobase + reg_offset); reg_offset 145 drivers/staging/comedi/drivers/comedi_8254.c val = readl(i8254->mmio + reg_offset); reg_offset 147 drivers/staging/comedi/drivers/comedi_8254.c val = inl(i8254->iobase + reg_offset); reg_offset 156 drivers/staging/comedi/drivers/comedi_8254.c unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; reg_offset 162 drivers/staging/comedi/drivers/comedi_8254.c writeb(val, i8254->mmio + reg_offset); reg_offset 164 drivers/staging/comedi/drivers/comedi_8254.c outb(val, i8254->iobase + reg_offset); reg_offset 168 drivers/staging/comedi/drivers/comedi_8254.c writew(val, i8254->mmio + reg_offset); reg_offset 170 drivers/staging/comedi/drivers/comedi_8254.c outw(val, i8254->iobase + reg_offset); reg_offset 174 drivers/staging/comedi/drivers/comedi_8254.c writel(val, i8254->mmio + reg_offset); reg_offset 176 drivers/staging/comedi/drivers/comedi_8254.c outl(val, i8254->iobase + reg_offset); reg_offset 39 drivers/tty/serial/8250/8250_early.c int reg_offset = offset; reg_offset 54 drivers/tty/serial/8250/8250_early.c return port->serial_in(port, reg_offset); reg_offset 62 drivers/tty/serial/8250/8250_early.c int reg_offset = offset; reg_offset 82 drivers/tty/serial/8250/8250_early.c port->serial_out(port, reg_offset, value); reg_offset 81 drivers/tty/serial/amba-pl011.c const u16 *reg_offset; reg_offset 104 drivers/tty/serial/amba-pl011.c .reg_offset = pl011_std_offsets, reg_offset 119 drivers/tty/serial/amba-pl011.c .reg_offset = pl011_std_offsets, reg_offset 134 drivers/tty/serial/amba-pl011.c .reg_offset = pl011_std_offsets, reg_offset 182 drivers/tty/serial/amba-pl011.c .reg_offset = pl011_st_offsets, reg_offset 218 drivers/tty/serial/amba-pl011.c .reg_offset = pl011_zte_offsets, reg_offset 263 drivers/tty/serial/amba-pl011.c const u16 *reg_offset; reg_offset 286 drivers/tty/serial/amba-pl011.c return uap->reg_offset[reg]; reg_offset 2637 drivers/tty/serial/amba-pl011.c uap->reg_offset = vendor->reg_offset; reg_offset 2731 drivers/tty/serial/amba-pl011.c uap->reg_offset = uap->vendor->reg_offset; reg_offset 366 drivers/tty/serial/mxs-auart.c const u16 *reg_offset; reg_offset 413 drivers/tty/serial/mxs-auart.c .reg_offset = mxs_asm9260_offsets, reg_offset 417 drivers/tty/serial/mxs-auart.c .reg_offset = mxs_stmp37xx_offsets, reg_offset 490 drivers/tty/serial/mxs-auart.c return uap->vendor->reg_offset[reg]; reg_offset 358 drivers/xen/xen-pciback/conf_space_header.c #define CFG_FIELD_BAR(reg_offset) \ reg_offset 360 drivers/xen/xen-pciback/conf_space_header.c .offset = reg_offset, \ reg_offset 369 drivers/xen/xen-pciback/conf_space_header.c #define CFG_FIELD_ROM(reg_offset) \ reg_offset 371 drivers/xen/xen-pciback/conf_space_header.c .offset = reg_offset, \ reg_offset 1161 include/linux/irq.h u32 val, int reg_offset) reg_offset 1164 include/linux/irq.h gc->reg_writel(val, gc->reg_base + reg_offset); reg_offset 1166 include/linux/irq.h writel(val, gc->reg_base + reg_offset); reg_offset 1170 include/linux/irq.h int reg_offset) reg_offset 1173 include/linux/irq.h return gc->reg_readl(gc->reg_base + reg_offset); reg_offset 1175 include/linux/irq.h return readl(gc->reg_base + reg_offset); reg_offset 97 include/linux/mfd/palmas.h int reg_offset; reg_offset 46 include/linux/platform_data/hsmmc-omap.h u16 reg_offset; reg_offset 38 include/linux/platform_data/mmc-omap.h u16 reg_offset; reg_offset 1137 include/linux/regmap.h unsigned int reg_offset; reg_offset 1143 include/linux/regmap.h [_irq] = { .reg_offset = (_off), .mask = (_mask) } reg_offset 1148 include/linux/regmap.h .reg_offset = (_id) / (_reg_bits), \ reg_offset 333 sound/pci/intel8x0.c unsigned long reg_offset; /* offset to bmaddr */ reg_offset 660 sound/pci/intel8x0.c unsigned long port = ichdev->reg_offset; reg_offset 712 sound/pci/intel8x0.c unsigned long port = ichdev->reg_offset; reg_offset 808 sound/pci/intel8x0.c unsigned long port = ichdev->reg_offset; reg_offset 845 sound/pci/intel8x0.c unsigned long port = ichdev->reg_offset; reg_offset 1018 sound/pci/intel8x0.c civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); reg_offset 1019 sound/pci/intel8x0.c ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); reg_offset 1025 sound/pci/intel8x0.c if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) reg_offset 1036 sound/pci/intel8x0.c if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) reg_offset 2535 sound/pci/intel8x0.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); reg_offset 2538 sound/pci/intel8x0.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); reg_offset 2542 sound/pci/intel8x0.c if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) reg_offset 2550 sound/pci/intel8x0.c iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, reg_offset 2563 sound/pci/intel8x0.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); reg_offset 2566 sound/pci/intel8x0.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); reg_offset 2648 sound/pci/intel8x0.c unsigned long port = ichdev->reg_offset; reg_offset 2702 sound/pci/intel8x0.c port = ichdev->reg_offset; reg_offset 2718 sound/pci/intel8x0.c civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); reg_offset 2719 sound/pci/intel8x0.c pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); reg_offset 2724 sound/pci/intel8x0.c if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && reg_offset 2725 sound/pci/intel8x0.c pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) reg_offset 3032 sound/pci/intel8x0.c ichdev->reg_offset = tbl[i].offset; reg_offset 3043 sound/pci/intel8x0.c ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; reg_offset 155 sound/pci/intel8x0m.c unsigned long reg_offset; /* offset to bmaddr */ reg_offset 384 sound/pci/intel8x0m.c unsigned long port = ichdev->reg_offset; reg_offset 434 sound/pci/intel8x0m.c unsigned long port = ichdev->reg_offset; reg_offset 526 sound/pci/intel8x0m.c unsigned long port = ichdev->reg_offset; reg_offset 573 sound/pci/intel8x0m.c ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; reg_offset 968 sound/pci/intel8x0m.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); reg_offset 971 sound/pci/intel8x0m.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); reg_offset 974 sound/pci/intel8x0m.c iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); reg_offset 986 sound/pci/intel8x0m.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); reg_offset 989 sound/pci/intel8x0m.c iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); reg_offset 1161 sound/pci/intel8x0m.c ichdev->reg_offset = tbl[i].offset; reg_offset 1172 sound/pci/intel8x0m.c ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; reg_offset 311 sound/pci/via82xx.c unsigned int reg_offset; reg_offset 974 sound/pci/via82xx.c ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) | reg_offset 1039 sound/pci/via82xx.c if (chip->spdif_on && viadev->reg_offset == 0x30) reg_offset 1050 sound/pci/via82xx.c outb(chip->playback_volume[viadev->reg_offset / 0x10][0], reg_offset 1052 sound/pci/via82xx.c outb(chip->playback_volume[viadev->reg_offset / 0x10][1], reg_offset 1180 sound/pci/via82xx.c if (chip->spdif_on && viadev->reg_offset == 0x30) { reg_offset 1184 sound/pci/via82xx.c } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { reg_offset 1188 sound/pci/via82xx.c } else if (chip->dxs_src && viadev->reg_offset < 0x40) { reg_offset 1251 sound/pci/via82xx.c stream = viadev->reg_offset / 0x10; reg_offset 1345 sound/pci/via82xx.c stream = viadev->reg_offset / 0x10; reg_offset 1422 sound/pci/via82xx.c static void init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset, reg_offset 1425 sound/pci/via82xx.c chip->devs[idx].reg_offset = reg_offset; reg_offset 1428 sound/pci/via82xx.c chip->devs[idx].port = chip->port + reg_offset; reg_offset 206 sound/pci/via82xx_modem.c unsigned int reg_offset; reg_offset 821 sound/pci/via82xx_modem.c static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset, reg_offset 824 sound/pci/via82xx_modem.c chip->devs[idx].reg_offset = reg_offset; reg_offset 826 sound/pci/via82xx_modem.c chip->devs[idx].port = chip->port + reg_offset; reg_offset 4992 sound/soc/codecs/wcd9335.c .reg_offset = 0, reg_offset 2139 sound/soc/codecs/wm8994.c int reg_offset, ret; reg_offset 2147 sound/soc/codecs/wm8994.c reg_offset = 0; reg_offset 2152 sound/soc/codecs/wm8994.c reg_offset = 0x20; reg_offset 2160 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset); reg_offset 2216 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, reg_offset 2222 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, reg_offset 2229 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset, reg_offset 2233 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset, reg_offset 2236 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset, reg_offset 2241 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset, reg_offset 2244 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, reg_offset 2247 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, reg_offset 2251 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, reg_offset 2289 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, reg_offset 1800 sound/soc/codecs/wm8995.c int reg_offset, ret; reg_offset 1815 sound/soc/codecs/wm8995.c reg_offset = 0; reg_offset 1819 sound/soc/codecs/wm8995.c reg_offset = 0x20; reg_offset 1865 sound/soc/codecs/wm8995.c snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, reg_offset 1870 sound/soc/codecs/wm8995.c snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset, reg_offset 1874 sound/soc/codecs/wm8995.c snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); reg_offset 1876 sound/soc/codecs/wm8995.c snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset, reg_offset 1880 sound/soc/codecs/wm8995.c snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset, reg_offset 1887 sound/soc/codecs/wm8995.c snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, reg_offset 43 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 154 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 208 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 332 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 420 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 530 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 623 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 651 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 673 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 772 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 816 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 855 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 920 sound/soc/fsl/fsl_sai.c if (sai->soc_data->reg_offset == 8) { reg_offset 1053 sound/soc/fsl/fsl_sai.c .reg_offset = 0, reg_offset 1060 sound/soc/fsl/fsl_sai.c .reg_offset = 0, reg_offset 1067 sound/soc/fsl/fsl_sai.c .reg_offset = 8, reg_offset 1074 sound/soc/fsl/fsl_sai.c .reg_offset = 8, reg_offset 1081 sound/soc/fsl/fsl_sai.c .reg_offset = 0, reg_offset 1117 sound/soc/fsl/fsl_sai.c unsigned int ofs = sai->soc_data->reg_offset; reg_offset 162 sound/soc/fsl/fsl_sai.h unsigned int reg_offset; reg_offset 27 sound/soc/rockchip/rockchip_i2s.c u32 reg_offset; reg_offset 367 sound/soc/rockchip/rockchip_i2s.c regmap_write(i2s->grf, i2s->pins->reg_offset, val); reg_offset 565 sound/soc/rockchip/rockchip_i2s.c .reg_offset = 0xe220, reg_offset 38 sound/soc/sh/rcar/gen.c unsigned int reg_offset; reg_offset 46 sound/soc/sh/rcar/gen.c .reg_offset = offset, \ reg_offset 191 sound/soc/sh/rcar/gen.c regf.reg = conf[i].reg_offset; reg_offset 1737 virt/kvm/arm/vgic/vgic-its.c .reg_offset = off, \ reg_offset 1746 virt/kvm/arm/vgic/vgic-its.c .reg_offset = off, \ reg_offset 450 virt/kvm/arm/vgic/vgic-mmio-v3.c .reg_offset = off, \ reg_offset 457 virt/kvm/arm/vgic/vgic-mmio-v3.c .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ reg_offset 663 virt/kvm/arm/vgic/vgic-mmio.c if (offset < region->reg_offset) reg_offset 666 virt/kvm/arm/vgic/vgic-mmio.c if (offset >= region->reg_offset + region->len) reg_offset 9 virt/kvm/arm/vgic/vgic-mmio.h unsigned int reg_offset; reg_offset 69 virt/kvm/arm/vgic/vgic-mmio.h .reg_offset = off, \ reg_offset 81 virt/kvm/arm/vgic/vgic-mmio.h .reg_offset = off, \ reg_offset 91 virt/kvm/arm/vgic/vgic-mmio.h .reg_offset = off, \