reg_off 404 arch/x86/events/intel/pt.c unsigned int reg_off; reg_off 409 arch/x86/events/intel/pt.c .reg_off = RTIT_CTL_ADDR0_OFFSET, reg_off 414 arch/x86/events/intel/pt.c .reg_off = RTIT_CTL_ADDR1_OFFSET, reg_off 419 arch/x86/events/intel/pt.c .reg_off = RTIT_CTL_ADDR2_OFFSET, reg_off 424 arch/x86/events/intel/pt.c .reg_off = RTIT_CTL_ADDR3_OFFSET, reg_off 463 arch/x86/events/intel/pt.c rtit_ctl |= filter->config << pt_address_ranges[range].reg_off; reg_off 393 arch/x86/kernel/unwind_orc.c static bool get_reg(struct unwind_state *state, unsigned int reg_off, reg_off 396 arch/x86/kernel/unwind_orc.c unsigned int reg = reg_off/8; reg_off 152 arch/x86/kvm/lapic.h static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) reg_off 154 arch/x86/kvm/lapic.h return *((u32 *) (apic->regs + reg_off)); reg_off 157 arch/x86/kvm/lapic.h static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) reg_off 159 arch/x86/kvm/lapic.h *((u32 *) (apic->regs + reg_off)) = val; reg_off 329 drivers/clk/clk-stm32mp1.c u32 reg_off; reg_off 340 drivers/clk/clk-stm32mp1.c u32 reg_off; reg_off 348 drivers/clk/clk-stm32mp1.c u32 reg_off; reg_off 391 drivers/clk/clk-stm32mp1.c gate_cfg->reg_off + base, reg_off 422 drivers/clk/clk-stm32mp1.c div_cfg->reg_off + base, reg_off 440 drivers/clk/clk-stm32mp1.c mux_cfg->reg_off + base, mux_cfg->shift, reg_off 485 drivers/clk/clk-stm32mp1.c mmux->mux.reg = cfg->mux->reg_off + base; reg_off 500 drivers/clk/clk-stm32mp1.c mux->reg = cfg->mux->reg_off + base; reg_off 523 drivers/clk/clk-stm32mp1.c div->reg = cfg->div->reg_off + base; reg_off 546 drivers/clk/clk-stm32mp1.c mgate->gate.reg = cfg->gate->reg_off + base; reg_off 561 drivers/clk/clk-stm32mp1.c gate->reg = cfg->gate->reg_off + base; reg_off 1099 drivers/clk/clk-stm32mp1.c .reg_off = _offset,\ reg_off 1127 drivers/clk/clk-stm32mp1.c .reg_off = _offset,\ reg_off 1148 drivers/clk/clk-stm32mp1.c .reg_off = _offset,\ reg_off 1199 drivers/clk/clk-stm32mp1.c .reg_off = _gate_offset,\ reg_off 1233 drivers/clk/clk-stm32mp1.c .reg_off = _div_offset,\ reg_off 1249 drivers/clk/clk-stm32mp1.c .reg_off = _offset,\ reg_off 1416 drivers/clk/clk-stm32mp1.c .reg_off = _gate_offset,\ reg_off 1600 drivers/clk/clk-stm32mp1.c .reg_off = _offset,\ reg_off 102 drivers/clk/meson/axg-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 107 drivers/clk/meson/axg-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 112 drivers/clk/meson/axg-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 117 drivers/clk/meson/axg-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 122 drivers/clk/meson/axg-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 203 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 208 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 250 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 255 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 260 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 367 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ reg_off 28 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 33 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 38 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 43 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL2, reg_off 48 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 53 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 92 drivers/clk/meson/axg.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 97 drivers/clk/meson/axg.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 102 drivers/clk/meson/axg.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 107 drivers/clk/meson/axg.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 112 drivers/clk/meson/axg.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 189 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 194 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 199 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 204 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL1, reg_off 209 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 214 drivers/clk/meson/axg.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 261 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL, reg_off 266 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL, reg_off 271 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL, reg_off 276 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL5, reg_off 281 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL, reg_off 286 drivers/clk/meson/axg.c .reg_off = HHI_HIFI_PLL_CNTL, reg_off 487 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL7, reg_off 492 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL7, reg_off 497 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL7, reg_off 502 drivers/clk/meson/axg.c .reg_off = HHI_PLL_TOP_MISC, reg_off 538 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL8, reg_off 543 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL8, reg_off 548 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL8, reg_off 553 drivers/clk/meson/axg.c .reg_off = HHI_PLL_TOP_MISC, reg_off 589 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL9, reg_off 594 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL9, reg_off 599 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL9, reg_off 604 drivers/clk/meson/axg.c .reg_off = HHI_MPLL_CNTL, reg_off 609 drivers/clk/meson/axg.c .reg_off = HHI_PLL_TOP_MISC, reg_off 645 drivers/clk/meson/axg.c .reg_off = HHI_MPLL3_CNTL0, reg_off 650 drivers/clk/meson/axg.c .reg_off = HHI_MPLL3_CNTL0, reg_off 655 drivers/clk/meson/axg.c .reg_off = HHI_MPLL3_CNTL0, reg_off 660 drivers/clk/meson/axg.c .reg_off = HHI_PLL_TOP_MISC, reg_off 714 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL, reg_off 719 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL, reg_off 724 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL, reg_off 729 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL1, reg_off 734 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL, reg_off 739 drivers/clk/meson/axg.c .reg_off = HHI_PCIE_PLL_CNTL, reg_off 58 drivers/clk/meson/clk-cpu-dyndiv.c return regmap_update_bits(clk->map, data->div.reg_off, reg_off 121 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 126 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 131 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 136 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 141 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 212 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_CEC_CLK_CNTL_REG0, reg_off 217 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_CEC_CLK_CNTL_REG0, reg_off 222 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_CEC_CLK_CNTL_REG1, reg_off 227 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_CEC_CLK_CNTL_REG1, reg_off 232 drivers/clk/meson/g12a-aoclk.c .reg_off = AO_CEC_CLK_CNTL_REG0, reg_off 32 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL0, reg_off 37 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL0, reg_off 42 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL0, reg_off 47 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL1, reg_off 52 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL0, reg_off 57 drivers/clk/meson/g12a.c .reg_off = HHI_FIX_PLL_CNTL0, reg_off 101 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_PLL_CNTL0, reg_off 106 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_PLL_CNTL0, reg_off 111 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_PLL_CNTL0, reg_off 116 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_PLL_CNTL0, reg_off 121 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_PLL_CNTL0, reg_off 160 drivers/clk/meson/g12a.c .reg_off = HHI_SYS1_PLL_CNTL0, reg_off 165 drivers/clk/meson/g12a.c .reg_off = HHI_SYS1_PLL_CNTL0, reg_off 170 drivers/clk/meson/g12a.c .reg_off = HHI_SYS1_PLL_CNTL0, reg_off 175 drivers/clk/meson/g12a.c .reg_off = HHI_SYS1_PLL_CNTL0, reg_off 180 drivers/clk/meson/g12a.c .reg_off = HHI_SYS1_PLL_CNTL0, reg_off 386 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_CPU_CLK_CNTL0, reg_off 391 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_CPU_CLK_CNTL0, reg_off 549 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_CPUB_CLK_CNTL, reg_off 554 drivers/clk/meson/g12a.c .reg_off = HHI_SYS_CPUB_CLK_CNTL, reg_off 1613 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL0, reg_off 1618 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL0, reg_off 1623 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL0, reg_off 1628 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL1, reg_off 1633 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL0, reg_off 1638 drivers/clk/meson/g12a.c .reg_off = HHI_GP0_PLL_CNTL0, reg_off 1678 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL0, reg_off 1683 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL0, reg_off 1688 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL0, reg_off 1693 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL1, reg_off 1698 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL0, reg_off 1703 drivers/clk/meson/g12a.c .reg_off = HHI_GP1_PLL_CNTL0, reg_off 1753 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL0, reg_off 1758 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL0, reg_off 1763 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL0, reg_off 1768 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL1, reg_off 1773 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL0, reg_off 1778 drivers/clk/meson/g12a.c .reg_off = HHI_HIFI_PLL_CNTL0, reg_off 1845 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL0, reg_off 1850 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL0, reg_off 1855 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL0, reg_off 1860 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL1, reg_off 1865 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL0, reg_off 1870 drivers/clk/meson/g12a.c .reg_off = HHI_PCIE_PLL_CNTL0, reg_off 1939 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL0, reg_off 1944 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL0, reg_off 1949 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL0, reg_off 1954 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL1, reg_off 1959 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL0, reg_off 1964 drivers/clk/meson/g12a.c .reg_off = HHI_HDMI_PLL_CNTL0, reg_off 2194 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL1, reg_off 2199 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL1, reg_off 2204 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL1, reg_off 2209 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL1, reg_off 2248 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL3, reg_off 2253 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL3, reg_off 2258 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL3, reg_off 2263 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL3, reg_off 2302 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL5, reg_off 2307 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL5, reg_off 2312 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL5, reg_off 2317 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL5, reg_off 2356 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL7, reg_off 2361 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL7, reg_off 2366 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL7, reg_off 2371 drivers/clk/meson/g12a.c .reg_off = HHI_MPLL_CNTL7, reg_off 2628 drivers/clk/meson/g12a.c .reg_off = HHI_VID_PLL_CLK_DIV, reg_off 2633 drivers/clk/meson/g12a.c .reg_off = HHI_VID_PLL_CLK_DIV, reg_off 88 drivers/clk/meson/gxbb-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 93 drivers/clk/meson/gxbb-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 98 drivers/clk/meson/gxbb-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 103 drivers/clk/meson/gxbb-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL1, reg_off 108 drivers/clk/meson/gxbb-aoclk.c .reg_off = AO_RTC_ALT_CLK_CNTL0, reg_off 88 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL, reg_off 93 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL, reg_off 98 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL, reg_off 103 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL2, reg_off 108 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL, reg_off 113 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL, reg_off 165 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 170 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 175 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 180 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL2, reg_off 185 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 190 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 213 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 218 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 223 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 234 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL2, reg_off 239 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 244 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, reg_off 375 drivers/clk/meson/gxbb.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 380 drivers/clk/meson/gxbb.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 385 drivers/clk/meson/gxbb.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 390 drivers/clk/meson/gxbb.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 395 drivers/clk/meson/gxbb.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 437 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 442 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 447 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 452 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 457 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 486 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 491 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 496 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 501 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL1, reg_off 506 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 511 drivers/clk/meson/gxbb.c .reg_off = HHI_GP0_PLL_CNTL, reg_off 717 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL7, reg_off 722 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL7, reg_off 727 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL7, reg_off 760 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL8, reg_off 765 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL8, reg_off 770 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL8, reg_off 803 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL9, reg_off 808 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL9, reg_off 813 drivers/clk/meson/gxbb.c .reg_off = HHI_MPLL_CNTL9, reg_off 1735 drivers/clk/meson/gxbb.c .reg_off = HHI_VID_PLL_CLK_DIV, reg_off 1740 drivers/clk/meson/gxbb.c .reg_off = HHI_VID_PLL_CLK_DIV, reg_off 67 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 72 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 77 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 82 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL2, reg_off 87 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 92 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 131 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL, reg_off 136 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL, reg_off 141 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL, reg_off 146 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL2, reg_off 151 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL, reg_off 156 drivers/clk/meson/meson8b.c .reg_off = HHI_VID_PLL_CNTL, reg_off 211 drivers/clk/meson/meson8b.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 216 drivers/clk/meson/meson8b.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 221 drivers/clk/meson/meson8b.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 226 drivers/clk/meson/meson8b.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 231 drivers/clk/meson/meson8b.c .reg_off = HHI_SYS_PLL_CNTL, reg_off 431 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL7, reg_off 436 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL7, reg_off 441 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL7, reg_off 446 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL, reg_off 481 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL8, reg_off 486 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL8, reg_off 491 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL8, reg_off 526 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL9, reg_off 531 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL9, reg_off 536 drivers/clk/meson/meson8b.c .reg_off = HHI_MPLL_CNTL9, reg_off 1921 drivers/clk/meson/meson8b.c .reg_off = HHI_GP_PLL_CNTL, reg_off 1926 drivers/clk/meson/meson8b.c .reg_off = HHI_GP_PLL_CNTL, reg_off 1931 drivers/clk/meson/meson8b.c .reg_off = HHI_GP_PLL_CNTL, reg_off 1936 drivers/clk/meson/meson8b.c .reg_off = HHI_GP_PLL_CNTL, reg_off 1941 drivers/clk/meson/meson8b.c .reg_off = HHI_GP_PLL_CNTL, reg_off 25 drivers/clk/meson/parm.h u16 reg_off; reg_off 34 drivers/clk/meson/parm.h regmap_read(map, p->reg_off, &val); reg_off 41 drivers/clk/meson/parm.h regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), reg_off 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2AC, .bit_off = 0}, reg_off 72 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2B4, .bit_off = 0}, reg_off 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2BC, .bit_off = 0}, reg_off 76 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2C4, .bit_off = 0}, reg_off 78 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2AC, .bit_off = 8}, reg_off 80 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2B4, .bit_off = 8}, reg_off 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2BC, .bit_off = 8}, reg_off 84 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .reg_off = 0x2C4, .bit_off = 8}, reg_off 404 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h u32 reg_off; reg_off 96 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c u32 reg_off, bit_off; reg_off 108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; reg_off 111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg_val = DPU_REG_READ(c, reg_off); reg_off 118 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, reg_off, new_val); reg_off 63 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c u32 reg_off, reg_off 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c name, c->blk_off + reg_off, val); reg_off 71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c writel_relaxed(val, c->base_off + c->blk_off + reg_off); reg_off 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) reg_off 76 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c return readl_relaxed(c->base_off + c->blk_off + reg_off); reg_off 301 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h u32 reg_off, reg_off 304 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); reg_off 59 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_off; reg_off 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; reg_off 76 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; reg_off 79 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_off 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); reg_off 90 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_off; reg_off 94 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_IN_RD_LIM_CONF0; reg_off 96 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_IN_WR_LIM_CONF0; reg_off 98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off += (xin_id / 4) * 4; reg_off 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_off 103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); reg_off 111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_off; reg_off 116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_IN_RD_LIM_CONF0; reg_off 118 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off = VBIF_IN_WR_LIM_CONF0; reg_off 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off += (xin_id / 4) * 4; reg_off 122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_off 767 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h u16 reg_off; reg_off 116 drivers/infiniband/hw/efa/efa_com.c read_resp->reg_off); reg_off 121 drivers/infiniband/hw/efa/efa_com.c if (read_resp->reg_off != offset) { reg_off 2969 drivers/iommu/arm-smmu-v3.c unsigned int reg_off, unsigned int ack_off) reg_off 2973 drivers/iommu/arm-smmu-v3.c writel_relaxed(val, smmu->base + reg_off); reg_off 82 drivers/irqchip/irq-davinci-aintc.c unsigned int irq_off, reg_off, prio, shift; reg_off 125 drivers/irqchip/irq-davinci-aintc.c for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; reg_off 126 drivers/irqchip/irq-davinci-aintc.c reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { reg_off 129 drivers/irqchip/irq-davinci-aintc.c davinci_aintc_writel(prio, reg_off); reg_off 156 drivers/irqchip/irq-davinci-aintc.c for (irq_off = 0, reg_off = 0; reg_off 158 drivers/irqchip/irq-davinci-aintc.c irq_off += 32, reg_off += 0x04) reg_off 159 drivers/irqchip/irq-davinci-aintc.c davinci_aintc_setup_gc(davinci_aintc_base + reg_off, reg_off 770 drivers/misc/habanalabs/goya/goya.c u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); reg_off 782 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); reg_off 783 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); reg_off 785 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); reg_off 786 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); reg_off 787 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); reg_off 789 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); reg_off 790 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); reg_off 791 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); reg_off 792 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); reg_off 793 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); reg_off 794 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); reg_off 795 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, reg_off 799 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); reg_off 800 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); reg_off 803 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED); reg_off 805 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); reg_off 807 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN); reg_off 808 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); reg_off 815 drivers/misc/habanalabs/goya/goya.c u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1); reg_off 822 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo); reg_off 823 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi); reg_off 824 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, reg_off 833 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr)); reg_off 834 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001); reg_off 1607 drivers/misc/habanalabs/goya/goya.c u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI); reg_off 1621 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr)); reg_off 1622 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr)); reg_off 1623 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH)); reg_off 1624 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); reg_off 1625 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); reg_off 1626 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0); reg_off 1627 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4); reg_off 1628 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8); reg_off 1629 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC); reg_off 1631 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); reg_off 1632 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); reg_off 1633 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); reg_off 1634 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); reg_off 1636 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); reg_off 1638 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); reg_off 1639 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); reg_off 1641 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, reg_off 1644 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN); reg_off 1646 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT); reg_off 1648 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE); reg_off 1656 drivers/misc/habanalabs/goya/goya.c u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1); reg_off 1668 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); reg_off 1669 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); reg_off 1670 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); reg_off 1671 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); reg_off 1673 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014); reg_off 1675 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); reg_off 1676 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); reg_off 1678 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off, reg_off 1681 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN); reg_off 1683 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT); reg_off 1685 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE); reg_off 217 drivers/mmc/host/cavium-octeon.c host->reg_off = 0; reg_off 85 drivers/mmc/host/cavium-thunderx.c host->reg_off = 0x2000; reg_off 37 drivers/mmc/host/cavium.h #define MIO_EMM_CFG(x) (0x00 + x->reg_off) reg_off 38 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off) reg_off 39 drivers/mmc/host/cavium.h #define MIO_EMM_DMA(x) (0x50 + x->reg_off) reg_off 40 drivers/mmc/host/cavium.h #define MIO_EMM_CMD(x) (0x58 + x->reg_off) reg_off 41 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off) reg_off 42 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off) reg_off 43 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off) reg_off 44 drivers/mmc/host/cavium.h #define MIO_EMM_INT(x) (0x78 + x->reg_off) reg_off 45 drivers/mmc/host/cavium.h #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off) reg_off 46 drivers/mmc/host/cavium.h #define MIO_EMM_WDOG(x) (0x88 + x->reg_off) reg_off 47 drivers/mmc/host/cavium.h #define MIO_EMM_SAMPLE(x) (0x90 + x->reg_off) reg_off 48 drivers/mmc/host/cavium.h #define MIO_EMM_STS_MASK(x) (0x98 + x->reg_off) reg_off 49 drivers/mmc/host/cavium.h #define MIO_EMM_RCA(x) (0xa0 + x->reg_off) reg_off 50 drivers/mmc/host/cavium.h #define MIO_EMM_INT_EN_SET(x) (0xb0 + x->reg_off) reg_off 51 drivers/mmc/host/cavium.h #define MIO_EMM_INT_EN_CLR(x) (0xb8 + x->reg_off) reg_off 52 drivers/mmc/host/cavium.h #define MIO_EMM_BUF_IDX(x) (0xe0 + x->reg_off) reg_off 53 drivers/mmc/host/cavium.h #define MIO_EMM_BUF_DAT(x) (0xe8 + x->reg_off) reg_off 59 drivers/mmc/host/cavium.h int reg_off; reg_off 698 drivers/mmc/host/sunxi-mmc.c static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) reg_off 712 drivers/mmc/host/sunxi-mmc.c writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); reg_off 807 drivers/mtd/nand/raw/qcom_nandc.c int reg_off, const void *vaddr, reg_off 821 drivers/mtd/nand/raw/qcom_nandc.c nandc_reg_phys(nandc, reg_off + 4 * i), reg_off 827 drivers/mtd/nand/raw/qcom_nandc.c nandc_reg_phys(nandc, reg_off + 4 * i), reg_off 893 drivers/mtd/nand/raw/qcom_nandc.c int reg_off, const void *vaddr, int size, reg_off 930 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.src_addr = nandc->base_dma + reg_off; reg_off 934 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.dst_addr = nandc->base_dma + reg_off; reg_off 1046 drivers/mtd/nand/raw/qcom_nandc.c static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, reg_off 1052 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); reg_off 1064 drivers/mtd/nand/raw/qcom_nandc.c static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, reg_off 1070 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); reg_off 1590 drivers/mtd/nand/raw/qcom_nandc.c int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; reg_off 1628 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, data_buf, data_size1, 0); reg_off 1629 drivers/mtd/nand/raw/qcom_nandc.c reg_off += data_size1; reg_off 1631 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); reg_off 1632 drivers/mtd/nand/raw/qcom_nandc.c reg_off += oob_size1; reg_off 1634 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); reg_off 1635 drivers/mtd/nand/raw/qcom_nandc.c reg_off += data_size2; reg_off 1637 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); reg_off 2092 drivers/mtd/nand/raw/qcom_nandc.c int reg_off = FLASH_BUF_ACC; reg_off 2107 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, data_buf, data_size1, reg_off 2109 drivers/mtd/nand/raw/qcom_nandc.c reg_off += data_size1; reg_off 2112 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, oob_buf, oob_size1, reg_off 2114 drivers/mtd/nand/raw/qcom_nandc.c reg_off += oob_size1; reg_off 2117 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, data_buf, data_size2, reg_off 2119 drivers/mtd/nand/raw/qcom_nandc.c reg_off += data_size2; reg_off 2122 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); reg_off 1025 drivers/net/ethernet/amazon/ena/ena_admin_defs.h u16 reg_off; reg_off 841 drivers/net/ethernet/amazon/ena/ena_com.c read_resp->reg_off); reg_off 846 drivers/net/ethernet/amazon/ena/ena_com.c if (read_resp->reg_off != offset) { reg_off 1918 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg_type, reg_off, val = 0; reg_off 1921 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = BNXT_FW_HEALTH_REG_OFF(reg); reg_off 1924 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_read_config_dword(bp->pdev, reg_off, &val); reg_off 1927 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = fw_health->mapped_regs[reg_idx]; reg_off 1930 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = readl(bp->bar0 + reg_off); reg_off 1933 drivers/net/ethernet/broadcom/bnxt/bnxt.c val = readl(bp->bar1 + reg_off); reg_off 10596 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg_type, reg_off, delay_msecs; reg_off 10600 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = BNXT_FW_HEALTH_REG_OFF(reg); reg_off 10603 drivers/net/ethernet/broadcom/bnxt/bnxt.c pci_write_config_dword(bp->pdev, reg_off, val); reg_off 10606 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(reg_off & BNXT_GRC_BASE_MASK, reg_off 10608 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; reg_off 10611 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(val, bp->bar0 + reg_off); reg_off 10614 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(val, bp->bar1 + reg_off); reg_off 752 drivers/net/ethernet/cavium/liquidio/octeon_device.h #define octeon_write_csr(oct_dev, reg_off, value) \ reg_off 753 drivers/net/ethernet/cavium/liquidio/octeon_device.h writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) reg_off 755 drivers/net/ethernet/cavium/liquidio/octeon_device.h #define octeon_write_csr64(oct_dev, reg_off, val64) \ reg_off 756 drivers/net/ethernet/cavium/liquidio/octeon_device.h writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) reg_off 758 drivers/net/ethernet/cavium/liquidio/octeon_device.h #define octeon_read_csr(oct_dev, reg_off) \ reg_off 759 drivers/net/ethernet/cavium/liquidio/octeon_device.h readl((oct_dev)->mmio[0].hw_addr + (reg_off)) reg_off 761 drivers/net/ethernet/cavium/liquidio/octeon_device.h #define octeon_read_csr64(oct_dev, reg_off) \ reg_off 762 drivers/net/ethernet/cavium/liquidio/octeon_device.h readq((oct_dev)->mmio[0].hw_addr + (reg_off)) reg_off 129 drivers/pinctrl/pinctrl-digicolor.c int bit_off, reg_off; reg_off 132 drivers/pinctrl/pinctrl-digicolor.c dc_client_sel(group, ®_off, &bit_off); reg_off 134 drivers/pinctrl/pinctrl-digicolor.c reg = readb_relaxed(pmap->regs + reg_off); reg_off 137 drivers/pinctrl/pinctrl-digicolor.c writeb_relaxed(reg, pmap->regs + reg_off); reg_off 147 drivers/pinctrl/pinctrl-digicolor.c int bit_off, reg_off; reg_off 150 drivers/pinctrl/pinctrl-digicolor.c dc_client_sel(offset, ®_off, &bit_off); reg_off 152 drivers/pinctrl/pinctrl-digicolor.c reg = readb_relaxed(pmap->regs + reg_off); reg_off 170 drivers/pinctrl/pinctrl-digicolor.c int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); reg_off 176 drivers/pinctrl/pinctrl-digicolor.c drive = readb_relaxed(pmap->regs + reg_off); reg_off 178 drivers/pinctrl/pinctrl-digicolor.c writeb_relaxed(drive, pmap->regs + reg_off); reg_off 190 drivers/pinctrl/pinctrl-digicolor.c int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); reg_off 198 drivers/pinctrl/pinctrl-digicolor.c drive = readb_relaxed(pmap->regs + reg_off); reg_off 200 drivers/pinctrl/pinctrl-digicolor.c writeb_relaxed(drive, pmap->regs + reg_off); reg_off 209 drivers/pinctrl/pinctrl-digicolor.c int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION); reg_off 213 drivers/pinctrl/pinctrl-digicolor.c input = readb_relaxed(pmap->regs + reg_off); reg_off 221 drivers/pinctrl/pinctrl-digicolor.c int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); reg_off 227 drivers/pinctrl/pinctrl-digicolor.c output = readb_relaxed(pmap->regs + reg_off); reg_off 232 drivers/pinctrl/pinctrl-digicolor.c writeb_relaxed(output, pmap->regs + reg_off); reg_off 83 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg_off 84 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); reg_off 92 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg_off 93 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); reg_off 95 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val | (1 << offset), reg_off); reg_off 101 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg_off 102 drivers/pinctrl/spear/pinctrl-plgpio.c u32 val = readl_relaxed(reg_off); reg_off 104 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val & ~(1 << offset), reg_off); reg_off 323 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off; reg_off 340 drivers/pinctrl/spear/pinctrl-plgpio.c reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); reg_off 341 drivers/pinctrl/spear/pinctrl-plgpio.c val = readl_relaxed(reg_off); reg_off 345 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val | (1 << offset), reg_off); reg_off 347 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(val & ~(1 << offset), reg_off); reg_off 377 drivers/rtc/rtc-sh.c static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) reg_off 382 drivers/rtc/rtc-sh.c byte = readb(rtc->regbase + reg_off); reg_off 415 drivers/rtc/rtc-sh.c int value, int reg_off) reg_off 419 drivers/rtc/rtc-sh.c writeb(0, rtc->regbase + reg_off); reg_off 421 drivers/rtc/rtc-sh.c writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); reg_off 1891 drivers/scsi/advansys.c #define AdvReadByteRegister(iop_base, reg_off) \ reg_off 1892 drivers/scsi/advansys.c (ADV_MEM_READB((iop_base) + (reg_off))) reg_off 1895 drivers/scsi/advansys.c #define AdvWriteByteRegister(iop_base, reg_off, byte) \ reg_off 1896 drivers/scsi/advansys.c (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) reg_off 1899 drivers/scsi/advansys.c #define AdvReadWordRegister(iop_base, reg_off) \ reg_off 1900 drivers/scsi/advansys.c (ADV_MEM_READW((iop_base) + (reg_off))) reg_off 1903 drivers/scsi/advansys.c #define AdvWriteWordRegister(iop_base, reg_off, word) \ reg_off 1904 drivers/scsi/advansys.c (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) reg_off 1907 drivers/scsi/advansys.c #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ reg_off 1908 drivers/scsi/advansys.c (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) reg_off 1409 drivers/scsi/bnx2fc/bnx2fc_hwi.c u32 reg_off; reg_off 1416 drivers/scsi/bnx2fc/bnx2fc_hwi.c reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF); reg_off 1417 drivers/scsi/bnx2fc/bnx2fc_hwi.c tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); reg_off 2706 drivers/scsi/bnx2i/bnx2i_hwi.c u32 reg_off; reg_off 2717 drivers/scsi/bnx2i/bnx2i_hwi.c reg_off = (1 << BNX2X_DB_SHIFT) * (cid_num & 0x1FFFF); reg_off 2718 drivers/scsi/bnx2i/bnx2i_hwi.c ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); reg_off 2730 drivers/scsi/bnx2i/bnx2i_hwi.c reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE reg_off 2734 drivers/scsi/bnx2i/bnx2i_hwi.c reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); reg_off 2737 drivers/scsi/bnx2i/bnx2i_hwi.c reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); reg_off 2739 drivers/scsi/bnx2i/bnx2i_hwi.c ep->qp.ctx_base = ioremap_nocache(ep->hba->reg_base + reg_off, reg_off 73 drivers/staging/vt6656/usbpipe.c int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) reg_off 76 drivers/staging/vt6656/usbpipe.c reg_off, reg, sizeof(u8), &data); reg_off 136 drivers/staging/vt6656/usbpipe.c int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data) reg_off 139 drivers/staging/vt6656/usbpipe.c reg_off, reg, sizeof(u8), data); reg_off 29 drivers/staging/vt6656/usbpipe.h int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data); reg_off 449 drivers/thermal/samsung/exynos_tmu.c unsigned int reg_off, j; reg_off 453 drivers/thermal/samsung/exynos_tmu.c reg_off = EXYNOS5433_THD_TEMP_RISE7_4; reg_off 456 drivers/thermal/samsung/exynos_tmu.c reg_off = EXYNOS5433_THD_TEMP_RISE3_0; reg_off 460 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + reg_off); reg_off 463 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + reg_off); reg_off 469 drivers/thermal/samsung/exynos_tmu.c unsigned int reg_off, j; reg_off 473 drivers/thermal/samsung/exynos_tmu.c reg_off = EXYNOS5433_THD_TEMP_FALL7_4; reg_off 476 drivers/thermal/samsung/exynos_tmu.c reg_off = EXYNOS5433_THD_TEMP_FALL3_0; reg_off 480 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + reg_off); reg_off 483 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + reg_off); reg_off 522 drivers/thermal/samsung/exynos_tmu.c unsigned int reg_off, bit_off; reg_off 525 drivers/thermal/samsung/exynos_tmu.c reg_off = ((7 - trip) / 2) * 4; reg_off 528 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); reg_off 531 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); reg_off 537 drivers/thermal/samsung/exynos_tmu.c unsigned int reg_off, bit_off; reg_off 540 drivers/thermal/samsung/exynos_tmu.c reg_off = ((7 - trip) / 2) * 4; reg_off 543 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); reg_off 546 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); reg_off 520 drivers/thermal/tegra/soctherm.c u32 r, reg_off; reg_off 529 drivers/thermal/tegra/soctherm.c reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); reg_off 543 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + reg_off); reg_off 549 drivers/thermal/tegra/soctherm.c writel(r, ts->regs + reg_off); reg_off 277 drivers/tty/serial/fsl_lpuart.c u8 reg_off; reg_off 293 drivers/tty/serial/fsl_lpuart.c .reg_off = IMX_REG_OFF, reg_off 299 drivers/tty/serial/fsl_lpuart.c .reg_off = IMX_REG_OFF, reg_off 2391 drivers/tty/serial/fsl_lpuart.c sport->port.membase += sdata->reg_off; reg_off 2481 kernel/bpf/verifier.c struct tnum reg_off; reg_off 2498 kernel/bpf/verifier.c reg_off = tnum_add(reg->var_off, tnum_const(ip_align + reg->off + off)); reg_off 2499 kernel/bpf/verifier.c if (!tnum_is_aligned(reg_off, size)) { reg_off 2517 kernel/bpf/verifier.c struct tnum reg_off; reg_off 2523 kernel/bpf/verifier.c reg_off = tnum_add(reg->var_off, tnum_const(reg->off + off)); reg_off 2524 kernel/bpf/verifier.c if (!tnum_is_aligned(reg_off, size)) { reg_off 42 sound/soc/xilinx/xlnx_i2s.c u32 reg_off, chan_id; reg_off 48 sound/soc/xilinx/xlnx_i2s.c reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); reg_off 49 sound/soc/xilinx/xlnx_i2s.c writel(chan_id, base + reg_off);