reg_divider_width  433 drivers/clk/clk-xgene.c 	u32 reg_divider_width;		/* Width of the bit to divider field */
reg_divider_width  543 drivers/clk/clk-xgene.c 		data &= (1 << pclk->param.reg_divider_width) - 1;
reg_divider_width  574 drivers/clk/clk-xgene.c 		divider &= (1 << pclk->param.reg_divider_width) - 1;
reg_divider_width  580 drivers/clk/clk-xgene.c 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)
reg_divider_width  715 drivers/clk/clk-xgene.c 				&parameters.reg_divider_width))
reg_divider_width  716 drivers/clk/clk-xgene.c 		parameters.reg_divider_width = 0;