reg_data2        1231 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	uint32_t reg_data2 = 0;
reg_data2        1308 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
reg_data2        1309 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
reg_data2        1310 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 				WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
reg_data2        1114 drivers/net/ethernet/intel/e1000e/80003es2lan.c 	u16 reg_data, reg_data2;
reg_data2        1135 drivers/net/ethernet/intel/e1000e/80003es2lan.c 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
reg_data2        1139 drivers/net/ethernet/intel/e1000e/80003es2lan.c 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
reg_data2        1159 drivers/net/ethernet/intel/e1000e/80003es2lan.c 	u16 reg_data, reg_data2;
reg_data2        1182 drivers/net/ethernet/intel/e1000e/80003es2lan.c 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
reg_data2        1186 drivers/net/ethernet/intel/e1000e/80003es2lan.c 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));