reg_ctrl 38 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c u8 reg_ctrl; reg_ctrl 53 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl = ret; reg_ctrl 56 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c if (mcu->reg_ctrl & MCU_CTRL_BTN) { reg_ctrl 58 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl & ~MCU_CTRL_BTN); reg_ctrl 79 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl = ret; reg_ctrl 92 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl | MCU_CTRL_POFF); reg_ctrl 103 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl &= ~bit; reg_ctrl 105 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl |= bit; reg_ctrl 107 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c i2c_smbus_write_byte_data(mcu->client, MCU_REG_CTRL, mcu->reg_ctrl); reg_ctrl 161 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c mcu->reg_ctrl = ret; reg_ctrl 801 drivers/gpu/drm/amd/amdgpu/vi.c u32 reg_ctrl; reg_ctrl 807 drivers/gpu/drm/amd/amdgpu/vi.c reg_ctrl = ixGNB_CLK3_DFS_CNTL; reg_ctrl 812 drivers/gpu/drm/amd/amdgpu/vi.c reg_ctrl = ixCG_ECLK_CNTL; reg_ctrl 833 drivers/gpu/drm/amd/amdgpu/vi.c tmp = RREG32_SMC(reg_ctrl); reg_ctrl 836 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(reg_ctrl, tmp); reg_ctrl 350 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; reg_ctrl 353 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c reg_ctrl = RD_CH_CTRL(ch); reg_ctrl 362 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_ctrl); reg_ctrl 553 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en; reg_ctrl 564 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c reg_ctrl = RD_CH_CTRL(ch); reg_ctrl 574 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((fmt << 16) & 0x1f0000, base + reg_ctrl); reg_ctrl 949 drivers/media/pci/cx23885/cx23885-core.c dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; reg_ctrl 959 drivers/media/pci/cx23885/cx23885-core.c dev->i2c_bus[1].reg_ctrl = I2C2_CTRL; reg_ctrl 969 drivers/media/pci/cx23885/cx23885-core.c dev->i2c_bus[2].reg_ctrl = I2C3_CTRL; reg_ctrl 84 drivers/media/pci/cx23885/cx23885-i2c.c cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); reg_ctrl 107 drivers/media/pci/cx23885/cx23885-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 129 drivers/media/pci/cx23885/cx23885-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 163 drivers/media/pci/cx23885/cx23885-i2c.c cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1); reg_ctrl 189 drivers/media/pci/cx23885/cx23885-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 241 drivers/media/pci/cx23885/cx23885.h u32 reg_ctrl; reg_ctrl 891 drivers/media/pci/cx25821/cx25821-core.c dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; reg_ctrl 83 drivers/media/pci/cx25821/cx25821-i2c.c cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2)); reg_ctrl 108 drivers/media/pci/cx25821/cx25821-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 134 drivers/media/pci/cx25821/cx25821-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 174 drivers/media/pci/cx25821/cx25821-i2c.c cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1); reg_ctrl 199 drivers/media/pci/cx25821/cx25821-i2c.c cx_write(bus->reg_ctrl, ctrl); reg_ctrl 150 drivers/media/pci/cx25821/cx25821.h u32 reg_ctrl; reg_ctrl 386 drivers/misc/lis3lv02d/lis3lv02d.c if (lis3->reg_ctrl) reg_ctrl 390 drivers/misc/lis3lv02d/lis3lv02d.c if (lis3->reg_ctrl) reg_ctrl 391 drivers/misc/lis3lv02d/lis3lv02d.c lis3->reg_ctrl(lis3, LIS3_REG_OFF); reg_ctrl 429 drivers/misc/lis3lv02d/lis3lv02d.c if (lis3->reg_ctrl) reg_ctrl 267 drivers/misc/lis3lv02d/lis3lv02d.h int (*reg_ctrl) (struct lis3lv02d *lis3, bool state); reg_ctrl 471 drivers/net/can/flexcan.c u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); reg_ctrl 473 drivers/net/can/flexcan.c priv->write(reg_ctrl, ®s->ctrl); reg_ctrl 479 drivers/net/can/flexcan.c u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); reg_ctrl 481 drivers/net/can/flexcan.c priv->write(reg_ctrl, ®s->ctrl); reg_ctrl 794 drivers/net/can/flexcan.c u32 reg_ctrl, reg_id, reg_iflag1; reg_ctrl 803 drivers/net/can/flexcan.c reg_ctrl = priv->read(&mb->can_ctrl); reg_ctrl 804 drivers/net/can/flexcan.c } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); reg_ctrl 807 drivers/net/can/flexcan.c code = reg_ctrl & FLEXCAN_MB_CODE_MASK; reg_ctrl 822 drivers/net/can/flexcan.c reg_ctrl = priv->read(&mb->can_ctrl); reg_ctrl 826 drivers/net/can/flexcan.c *timestamp = reg_ctrl << 16; reg_ctrl 829 drivers/net/can/flexcan.c if (reg_ctrl & FLEXCAN_MB_CNT_IDE) reg_ctrl 834 drivers/net/can/flexcan.c if (reg_ctrl & FLEXCAN_MB_CNT_RTR) reg_ctrl 836 drivers/net/can/flexcan.c cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); reg_ctrl 921 drivers/net/can/flexcan.c u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); reg_ctrl 925 drivers/net/can/flexcan.c 0, reg_ctrl << 16); reg_ctrl 1043 drivers/net/can/flexcan.c u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; reg_ctrl 1117 drivers/net/can/flexcan.c reg_ctrl = priv->read(®s->ctrl); reg_ctrl 1118 drivers/net/can/flexcan.c reg_ctrl &= ~FLEXCAN_CTRL_TSYN; reg_ctrl 1119 drivers/net/can/flexcan.c reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | reg_ctrl 1128 drivers/net/can/flexcan.c reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; reg_ctrl 1130 drivers/net/can/flexcan.c reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; reg_ctrl 1133 drivers/net/can/flexcan.c priv->reg_ctrl_default = reg_ctrl; reg_ctrl 1135 drivers/net/can/flexcan.c reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL; reg_ctrl 1136 drivers/net/can/flexcan.c netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); reg_ctrl 1137 drivers/net/can/flexcan.c priv->write(reg_ctrl, ®s->ctrl); reg_ctrl 124 drivers/net/wireless/ath/wcn36xx/dxe.c wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L; reg_ctrl 125 drivers/net/wireless/ath/wcn36xx/dxe.c wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H; reg_ctrl 775 drivers/net/wireless/ath/wcn36xx/dxe.c ch->reg_ctrl, ch->def_ctrl); reg_ctrl 443 drivers/net/wireless/ath/wcn36xx/dxe.h u32 reg_ctrl; reg_ctrl 43 drivers/spi/spi-ath79.c u32 reg_ctrl; reg_ctrl 90 drivers/spi/spi-ath79.c sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); reg_ctrl 103 drivers/spi/spi-ath79.c ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); reg_ctrl 115 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c config->reg_ctrl = params->etmv3.reg_ctrl; reg_ctrl 25 tools/perf/util/cs-etm-decoder/cs-etm-decoder.h u32 reg_ctrl; reg_ctrl 386 tools/perf/util/cs-etm.c t_params[idx].etmv3.reg_ctrl = metadata[idx][CS_ETM_ETMCR];