reg_clk_offset    426 drivers/clk/clk-xgene.c 	u32 reg_clk_offset;		/* Offset to clock enable CSR */
reg_clk_offset    457 drivers/clk/clk-xgene.c 					pclk->param.reg_clk_offset);
reg_clk_offset    460 drivers/clk/clk-xgene.c 					pclk->param.reg_clk_offset);
reg_clk_offset    463 drivers/clk/clk-xgene.c 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
reg_clk_offset    504 drivers/clk/clk-xgene.c 					pclk->param.reg_clk_offset);
reg_clk_offset    507 drivers/clk/clk-xgene.c 					pclk->param.reg_clk_offset);
reg_clk_offset    522 drivers/clk/clk-xgene.c 					pclk->param.reg_clk_offset);
reg_clk_offset    707 drivers/clk/clk-xgene.c 				&parameters.reg_clk_offset))
reg_clk_offset    708 drivers/clk/clk-xgene.c 		parameters.reg_clk_offset = 0x8;