reg_clk_mask      427 drivers/clk/clk-xgene.c 	u32 reg_clk_mask;		/* Mask bit for clock enable */
reg_clk_mask      458 drivers/clk/clk-xgene.c 		data |= pclk->param.reg_clk_mask;
reg_clk_mask      463 drivers/clk/clk-xgene.c 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
reg_clk_mask      505 drivers/clk/clk-xgene.c 		data &= ~pclk->param.reg_clk_mask;
reg_clk_mask      524 drivers/clk/clk-xgene.c 			data & pclk->param.reg_clk_mask ? "enabled" :
reg_clk_mask      530 drivers/clk/clk-xgene.c 	return data & pclk->param.reg_clk_mask ? 1 : 0;
reg_clk_mask      709 drivers/clk/clk-xgene.c 	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))
reg_clk_mask      710 drivers/clk/clk-xgene.c 		parameters.reg_clk_mask = 0xF;