reg_block        1591 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 					ATOM_INIT_REG_BLOCK *reg_block =
reg_block        1596 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 						((u8 *)reg_block + (2 * sizeof(u16)) +
reg_block        1597 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 						 le16_to_cpu(reg_block->usRegIndexTblSize));
reg_block        1598 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 					ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
reg_block        1599 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 					num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
reg_block        1636 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 							((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
reg_block         189 drivers/gpu/drm/amd/amdgpu/atom.c 		idx += gctx->reg_block;
reg_block         256 drivers/gpu/drm/amd/amdgpu/atom.c 			val = gctx->reg_block;
reg_block         461 drivers/gpu/drm/amd/amdgpu/atom.c 		idx += gctx->reg_block;
reg_block         523 drivers/gpu/drm/amd/amdgpu/atom.c 			gctx->reg_block = val;
reg_block         912 drivers/gpu/drm/amd/amdgpu/atom.c 	ctx->ctx->reg_block = U16(*ptr);
reg_block         914 drivers/gpu/drm/amd/amdgpu/atom.c 	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
reg_block        1270 drivers/gpu/drm/amd/amdgpu/atom.c 	ctx->reg_block = 0;
reg_block         138 drivers/gpu/drm/amd/amdgpu/atom.h 	uint16_t reg_block;
reg_block        2796 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	u32 reg_block, interrupt_mask;
reg_block        2805 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC0_REGISTER_OFFSET;
reg_block        2808 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC1_REGISTER_OFFSET;
reg_block        2811 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC2_REGISTER_OFFSET;
reg_block        2814 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC3_REGISTER_OFFSET;
reg_block        2817 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC4_REGISTER_OFFSET;
reg_block        2820 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		reg_block = SI_CRTC5_REGISTER_OFFSET;
reg_block        2829 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		interrupt_mask = RREG32(mmINT_MASK + reg_block);
reg_block        2831 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmINT_MASK + reg_block, interrupt_mask);
reg_block        2834 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		interrupt_mask = RREG32(mmINT_MASK + reg_block);
reg_block        2836 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmINT_MASK + reg_block, interrupt_mask);
reg_block        2844 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	u32 reg_block, lb_interrupt_mask;
reg_block        2853 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC0_REGISTER_OFFSET;
reg_block        2856 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC1_REGISTER_OFFSET;
reg_block        2859 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC2_REGISTER_OFFSET;
reg_block        2862 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC3_REGISTER_OFFSET;
reg_block        2865 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC4_REGISTER_OFFSET;
reg_block        2868 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC5_REGISTER_OFFSET;
reg_block        2877 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
reg_block        2879 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
reg_block        2882 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
reg_block        2884 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
reg_block        2895 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	u32 reg_block, lb_interrupt_mask;
reg_block        2904 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC0_REGISTER_OFFSET;
reg_block        2907 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC1_REGISTER_OFFSET;
reg_block        2910 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC2_REGISTER_OFFSET;
reg_block        2913 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC3_REGISTER_OFFSET;
reg_block        2916 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC4_REGISTER_OFFSET;
reg_block        2919 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		reg_block = CRTC5_REGISTER_OFFSET;
reg_block        2928 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
reg_block        2930 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
reg_block        2933 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
reg_block        2935 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
reg_block          49 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		ATOM_INIT_REG_BLOCK *reg_block,
reg_block          55 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize));
reg_block          84 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 			((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ;
reg_block         102 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		ATOM_INIT_REG_BLOCK *reg_block,
reg_block         106 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize))
reg_block         108 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
reg_block         138 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	ATOM_INIT_REG_BLOCK *reg_block;
reg_block         156 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		reg_block = (ATOM_INIT_REG_BLOCK *)
reg_block         158 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		result = atomctrl_set_mc_reg_address_table(reg_block, table);
reg_block         163 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 					reg_block, table);
reg_block         195 drivers/gpu/drm/radeon/atom.c 		idx += gctx->reg_block;
reg_block         262 drivers/gpu/drm/radeon/atom.c 			val = gctx->reg_block;
reg_block         467 drivers/gpu/drm/radeon/atom.c 		idx += gctx->reg_block;
reg_block         529 drivers/gpu/drm/radeon/atom.c 			gctx->reg_block = val;
reg_block         883 drivers/gpu/drm/radeon/atom.c 	ctx->ctx->reg_block = U16(*ptr);
reg_block         885 drivers/gpu/drm/radeon/atom.c 	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
reg_block        1227 drivers/gpu/drm/radeon/atom.c 	ctx->reg_block = 0;
reg_block         136 drivers/gpu/drm/radeon/atom.h 	uint16_t reg_block;
reg_block        4009 drivers/gpu/drm/radeon/radeon_atombios.c 					ATOM_INIT_REG_BLOCK *reg_block =
reg_block        4014 drivers/gpu/drm/radeon/radeon_atombios.c 						((u8 *)reg_block + (2 * sizeof(u16)) +
reg_block        4015 drivers/gpu/drm/radeon/radeon_atombios.c 						 le16_to_cpu(reg_block->usRegIndexTblSize));
reg_block        4016 drivers/gpu/drm/radeon/radeon_atombios.c 					ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
reg_block        4017 drivers/gpu/drm/radeon/radeon_atombios.c 					num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
reg_block        4054 drivers/gpu/drm/radeon/radeon_atombios.c 							((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
reg_block        1059 drivers/net/ethernet/intel/i40e/i40e_common.c 	u32 reg_block = 0;
reg_block        1063 drivers/net/ethernet/intel/i40e/i40e_common.c 		reg_block = abs_queue_idx / 128;
reg_block        1067 drivers/net/ethernet/intel/i40e/i40e_common.c 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
reg_block        1076 drivers/net/ethernet/intel/i40e/i40e_common.c 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
reg_block        1379 drivers/net/ethernet/intel/i40e/i40e_common.c 		u32 reg_block = 0;
reg_block        1382 drivers/net/ethernet/intel/i40e/i40e_common.c 			reg_block = abs_queue_idx / 128;
reg_block        1386 drivers/net/ethernet/intel/i40e/i40e_common.c 		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
reg_block        1391 drivers/net/ethernet/intel/i40e/i40e_common.c 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);