reg_base 29 arch/arm/mach-rockchip/rockchip.c void __iomem *reg_base; reg_base 36 arch/arm/mach-rockchip/rockchip.c reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); reg_base 37 arch/arm/mach-rockchip/rockchip.c if (reg_base) { reg_base 38 arch/arm/mach-rockchip/rockchip.c writel(0, reg_base + 0x30); reg_base 39 arch/arm/mach-rockchip/rockchip.c writel(0xffffffff, reg_base + 0x20); reg_base 40 arch/arm/mach-rockchip/rockchip.c writel(0xffffffff, reg_base + 0x24); reg_base 41 arch/arm/mach-rockchip/rockchip.c writel(1, reg_base + 0x30); reg_base 43 arch/arm/mach-rockchip/rockchip.c iounmap(reg_base); reg_base 114 arch/arm/mach-s3c24xx/common.h void __iomem *reg_base); reg_base 118 arch/arm/mach-s3c24xx/common.h unsigned long ext_f, void __iomem *reg_base); reg_base 123 arch/arm/mach-s3c24xx/common.h void __iomem *reg_base); reg_base 26 arch/arm/mach-s3c64xx/common.h unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base); reg_base 30 arch/powerpc/boot/ns16550.c static unsigned char *reg_base; reg_base 35 arch/powerpc/boot/ns16550.c out_8(reg_base + (UART_FCR << reg_shift), 0x06); reg_base 41 arch/powerpc/boot/ns16550.c while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); reg_base 42 arch/powerpc/boot/ns16550.c out_8(reg_base, c); reg_base 47 arch/powerpc/boot/ns16550.c while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); reg_base 48 arch/powerpc/boot/ns16550.c return in_8(reg_base); reg_base 53 arch/powerpc/boot/ns16550.c return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); reg_base 61 arch/powerpc/boot/ns16550.c if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) reg_base 66 arch/powerpc/boot/ns16550.c reg_base += reg_offset; reg_base 29 arch/powerpc/boot/uartlite.c static void * reg_base; reg_base 34 arch/powerpc/boot/uartlite.c out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX); reg_base 42 arch/powerpc/boot/uartlite.c reg = in_be32(reg_base + ULITE_STATUS); reg_base 43 arch/powerpc/boot/uartlite.c out_be32(reg_base + ULITE_TX, c); reg_base 50 arch/powerpc/boot/uartlite.c reg = in_be32(reg_base + ULITE_STATUS); reg_base 51 arch/powerpc/boot/uartlite.c return in_be32(reg_base + ULITE_RX); reg_base 56 arch/powerpc/boot/uartlite.c u32 reg = in_be32(reg_base + ULITE_STATUS); reg_base 65 arch/powerpc/boot/uartlite.c n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base)); reg_base 66 arch/powerpc/boot/uartlite.c if (n != sizeof(reg_base)) { reg_base 70 arch/powerpc/boot/uartlite.c reg_base = (void *)reg_phys; reg_base 27 arch/powerpc/boot/virtex.c unsigned char *reg_base; reg_base 32 arch/powerpc/boot/virtex.c if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) reg_base 37 arch/powerpc/boot/virtex.c reg_base += reg_offset; reg_base 55 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); reg_base 58 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); reg_base 59 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); reg_base 62 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); reg_base 65 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); reg_base 68 arch/powerpc/boot/virtex.c out_8(reg_base + (UART_FCR << reg_shift), reg_base 198 arch/powerpc/kvm/mpic.c gpa_t reg_base; reg_base 1390 arch/powerpc/kvm/mpic.c ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); reg_base 1431 arch/powerpc/kvm/mpic.c ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, reg_base 1451 arch/powerpc/kvm/mpic.c opp->reg_base, OPENPIC_REG_SIZE, reg_base 1473 arch/powerpc/kvm/mpic.c if (base == opp->reg_base) reg_base 1479 arch/powerpc/kvm/mpic.c opp->reg_base = base; reg_base 1569 arch/powerpc/kvm/mpic.c attr64 = opp->reg_base; reg_base 94 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; reg_base 99 arch/powerpc/platforms/powernv/opal-xscom.c reg_base = off >> 3; reg_base 103 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_read(ent->chip, reg_base, reg, &val); reg_base 125 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; reg_base 130 arch/powerpc/platforms/powernv/opal-xscom.c reg_base = off >> 3; reg_base 136 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_write(ent->chip, reg_base, reg, val); reg_base 173 arch/sh/drivers/pci/pci-sh4.h __raw_writel(val, chan->reg_base + reg); reg_base 179 arch/sh/drivers/pci/pci-sh4.h return __raw_readl(chan->reg_base + reg); reg_base 83 arch/sh/drivers/pci/pci-sh7751.c chan->reg_base = 0xfe200000; reg_base 100 arch/sh/drivers/pci/pci-sh7780.c addr = __raw_readl(hose->reg_base + SH4_PCIALR); reg_base 105 arch/sh/drivers/pci/pci-sh7780.c status = __raw_readw(hose->reg_base + PCI_STATUS); reg_base 113 arch/sh/drivers/pci/pci-sh7780.c __raw_writew(cmd, hose->reg_base + PCI_STATUS); reg_base 119 arch/sh/drivers/pci/pci-sh7780.c status = __raw_readl(hose->reg_base + SH4_PCIAINT); reg_base 127 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); reg_base 132 arch/sh/drivers/pci/pci-sh7780.c status = __raw_readl(hose->reg_base + SH4_PCIINT); reg_base 140 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(cmd, hose->reg_base + SH4_PCIINT); reg_base 154 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); reg_base 169 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, hose->reg_base + SH4_PCIAINT); reg_base 177 arch/sh/drivers/pci/pci-sh7780.c PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); reg_base 202 arch/sh/drivers/pci/pci-sh7780.c SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM); reg_base 210 arch/sh/drivers/pci/pci-sh7780.c SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM); reg_base 229 arch/sh/drivers/pci/pci-sh7780.c tmp = __raw_readl(hose->reg_base + SH4_PCICR); reg_base 231 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(tmp, hose->reg_base + SH4_PCICR); reg_base 234 arch/sh/drivers/pci/pci-sh7780.c tmp = __raw_readw(hose->reg_base + PCI_STATUS); reg_base 236 arch/sh/drivers/pci/pci-sh7780.c __raw_writew(tmp, hose->reg_base + PCI_STATUS); reg_base 239 arch/sh/drivers/pci/pci-sh7780.c tmp = __raw_readl(hose->reg_base + SH4_PCICR); reg_base 241 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(tmp, hose->reg_base + SH4_PCICR); reg_base 255 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base = 0xfe040000; reg_base 262 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH4_PCICR); reg_base 271 arch/sh/drivers/pci/pci-sh7780.c id = __raw_readw(chan->reg_base + PCI_VENDOR_ID); reg_base 277 arch/sh/drivers/pci/pci-sh7780.c id = __raw_readw(chan->reg_base + PCI_DEVICE_ID); reg_base 291 arch/sh/drivers/pci/pci-sh7780.c __raw_readb(chan->reg_base + PCI_REVISION_ID)); reg_base 298 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH4_PCICR); reg_base 308 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1); reg_base 310 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH4_PCILSR1); reg_base 316 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH4_PCILAR1); reg_base 317 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH4_PCILSR1); reg_base 324 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(memphys, chan->reg_base + SH4_PCILAR0); reg_base 326 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH4_PCILSR0); reg_base 338 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCICSCR0); reg_base 339 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCICSAR0); reg_base 340 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCICSCR1); reg_base 341 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCICSAR1); reg_base 369 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH7780_PCIMBMR(i - 1)); reg_base 370 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1)); reg_base 376 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0); reg_base 377 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCIIOBR); reg_base 378 arch/sh/drivers/pci/pci-sh7780.c __raw_writel(0, chan->reg_base + SH7780_PCIIOBMR); reg_base 382 arch/sh/drivers/pci/pci-sh7780.c PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND); reg_base 390 arch/sh/drivers/pci/pci-sh7780.c chan->reg_base + SH4_PCICR); reg_base 399 arch/sh/drivers/pci/pci-sh7780.c (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ? reg_base 119 arch/sh/drivers/pci/pcie-sh7786.c .reg_base = start, \ reg_base 238 arch/sh/drivers/pci/pcie-sh7786.c clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); reg_base 568 arch/sh/drivers/pci/pcie-sh7786.h __raw_writel(val, chan->reg_base + reg); reg_base 574 arch/sh/drivers/pci/pcie-sh7786.h return __raw_readl(chan->reg_base + reg); reg_base 29 arch/sh/include/asm/pci.h unsigned long reg_base; reg_base 652 arch/sparc/kernel/prom_irqtrans.c unsigned long reg_base = (unsigned long) _data; reg_base 673 arch/sparc/kernel/prom_irqtrans.c imap += reg_base; reg_base 686 arch/sparc/kernel/prom_irqtrans.c iclr = reg_base + SYSIO_ICLR_SLOT0; reg_base 689 arch/sparc/kernel/prom_irqtrans.c iclr = reg_base + SYSIO_ICLR_SLOT1; reg_base 692 arch/sparc/kernel/prom_irqtrans.c iclr = reg_base + SYSIO_ICLR_SLOT2; reg_base 696 arch/sparc/kernel/prom_irqtrans.c iclr = reg_base + SYSIO_ICLR_SLOT3; reg_base 213 arch/sparc/kernel/sbus.c unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; reg_base 223 arch/sparc/kernel/sbus.c imap += reg_base; reg_base 238 arch/sparc/kernel/sbus.c iclr = reg_base + SYSIO_ICLR_SLOT0; reg_base 241 arch/sparc/kernel/sbus.c iclr = reg_base + SYSIO_ICLR_SLOT1; reg_base 244 arch/sparc/kernel/sbus.c iclr = reg_base + SYSIO_ICLR_SLOT2; reg_base 248 arch/sparc/kernel/sbus.c iclr = reg_base + SYSIO_ICLR_SLOT3; reg_base 275 arch/sparc/kernel/sbus.c unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; reg_base 280 arch/sparc/kernel/sbus.c afsr_reg = reg_base + SYSIO_UE_AFSR; reg_base 281 arch/sparc/kernel/sbus.c afar_reg = reg_base + SYSIO_UE_AFAR; reg_base 349 arch/sparc/kernel/sbus.c unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; reg_base 354 arch/sparc/kernel/sbus.c afsr_reg = reg_base + SYSIO_CE_AFSR; reg_base 355 arch/sparc/kernel/sbus.c afar_reg = reg_base + SYSIO_CE_AFAR; reg_base 428 arch/sparc/kernel/sbus.c unsigned long afsr_reg, afar_reg, reg_base; reg_base 432 arch/sparc/kernel/sbus.c reg_base = iommu->write_complete_reg - 0x2000UL; reg_base 433 arch/sparc/kernel/sbus.c afsr_reg = reg_base + SYSIO_SBUS_AFSR; reg_base 434 arch/sparc/kernel/sbus.c afar_reg = reg_base + SYSIO_SBUS_AFAR; reg_base 497 arch/sparc/kernel/sbus.c unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; reg_base 532 arch/sparc/kernel/sbus.c reg_base + ECC_CONTROL); reg_base 546 arch/sparc/kernel/sbus.c unsigned long regs, reg_base; reg_base 567 arch/sparc/kernel/sbus.c reg_base = regs + SYSIO_IOMMUREG_BASE; reg_base 568 arch/sparc/kernel/sbus.c iommu->iommu_control = reg_base + IOMMU_CONTROL; reg_base 569 arch/sparc/kernel/sbus.c iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE; reg_base 570 arch/sparc/kernel/sbus.c iommu->iommu_flush = reg_base + IOMMU_FLUSH; reg_base 574 arch/sparc/kernel/sbus.c reg_base = regs + SYSIO_STRBUFREG_BASE; reg_base 575 arch/sparc/kernel/sbus.c strbuf->strbuf_control = reg_base + STRBUF_CONTROL; reg_base 576 arch/sparc/kernel/sbus.c strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH; reg_base 577 arch/sparc/kernel/sbus.c strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC; reg_base 41 arch/x86/platform/intel-quark/imr.c int reg_base; reg_base 110 arch/x86/platform/intel-quark/imr.c u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; reg_base 142 arch/x86/platform/intel-quark/imr.c u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; reg_base 587 arch/x86/platform/intel-quark/imr.c idev->reg_base = QUARK_X1000_IMR_REGBASE; reg_base 49 drivers/ata/ahci_brcm.c #define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18) reg_base 62 drivers/ata/ahci_qoriq.c struct ccsr_ahci *reg_base; reg_base 166 drivers/ata/ahci_qoriq.c void __iomem *reg_base = hpriv->mmio; reg_base 174 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 175 drivers/ata/ahci_qoriq.c writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); reg_base 176 drivers/ata/ahci_qoriq.c writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); reg_base 177 drivers/ata/ahci_qoriq.c writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); reg_base 178 drivers/ata/ahci_qoriq.c writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); reg_base 179 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 182 drivers/ata/ahci_qoriq.c reg_base + LS1021A_AXICC_ADDR); reg_base 192 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 193 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); reg_base 194 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); reg_base 195 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 197 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); reg_base 201 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 202 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); reg_base 203 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); reg_base 204 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 206 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); reg_base 216 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 217 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); reg_base 218 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); reg_base 219 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 221 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); reg_base 233 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 234 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); reg_base 235 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); reg_base 236 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 238 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); reg_base 242 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); reg_base 243 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); reg_base 244 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); reg_base 245 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); reg_base 247 drivers/ata/ahci_qoriq.c writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); reg_base 86 drivers/ata/ahci_sunxi.c static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) reg_base 92 drivers/ata/ahci_sunxi.c writel(0, reg_base + AHCI_RWCR); reg_base 95 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); reg_base 96 drivers/ata/ahci_sunxi.c sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, reg_base 99 drivers/ata/ahci_sunxi.c sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, reg_base 102 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); reg_base 103 drivers/ata/ahci_sunxi.c sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); reg_base 104 drivers/ata/ahci_sunxi.c sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, reg_base 106 drivers/ata/ahci_sunxi.c sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, reg_base 110 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); reg_base 114 drivers/ata/ahci_sunxi.c reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28); reg_base 125 drivers/ata/ahci_sunxi.c sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); reg_base 129 drivers/ata/ahci_sunxi.c reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24); reg_base 142 drivers/ata/ahci_sunxi.c writel(0x7, reg_base + AHCI_RWCR); reg_base 38 drivers/clk/mvebu/clk-cpu.c void __iomem *reg_base; reg_base 54 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); reg_base 83 drivers/clk/mvebu/clk-cpu.c reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) reg_base 86 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); reg_base 90 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) reg_base 92 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg_base 95 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) reg_base 97 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg_base 102 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg_base 124 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); reg_base 143 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg_base 146 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg_base 213 drivers/clk/mvebu/clk-cpu.c cpuclk[cpu].reg_base = clock_complex_base; reg_base 206 drivers/clk/nxp/clk-lpc18xx-ccu.c void __iomem *reg_base, reg_base 218 drivers/clk/nxp/clk-lpc18xx-ccu.c div->reg = branch->offset + reg_base; reg_base 227 drivers/clk/nxp/clk-lpc18xx-ccu.c branch->gate.reg = branch->offset + reg_base; reg_base 250 drivers/clk/nxp/clk-lpc18xx-ccu.c static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base, reg_base 260 drivers/clk/nxp/clk-lpc18xx-ccu.c lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base, reg_base 271 drivers/clk/nxp/clk-lpc18xx-ccu.c void __iomem *reg_base; reg_base 274 drivers/clk/nxp/clk-lpc18xx-ccu.c reg_base = of_iomap(np, 0); reg_base 275 drivers/clk/nxp/clk-lpc18xx-ccu.c if (!reg_base) { reg_base 282 drivers/clk/nxp/clk-lpc18xx-ccu.c iounmap(reg_base); reg_base 289 drivers/clk/nxp/clk-lpc18xx-ccu.c iounmap(reg_base); reg_base 303 drivers/clk/nxp/clk-lpc18xx-ccu.c lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]); reg_base 555 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg_base, int n) reg_base 557 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n); reg_base 644 drivers/clk/nxp/clk-lpc18xx-cgu.c static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base) reg_base 650 drivers/clk/nxp/clk-lpc18xx-cgu.c reg_base, i); reg_base 658 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg_base; reg_base 660 drivers/clk/nxp/clk-lpc18xx-cgu.c reg_base = of_iomap(np, 0); reg_base 661 drivers/clk/nxp/clk-lpc18xx-cgu.c if (!reg_base) { reg_base 666 drivers/clk/nxp/clk-lpc18xx-cgu.c lpc18xx_cgu_register_source_clks(np, reg_base); reg_base 667 drivers/clk/nxp/clk-lpc18xx-cgu.c lpc18xx_cgu_register_base_clks(reg_base); reg_base 505 drivers/clk/pistachio/clk-pll.c 0, p->base + pll[i].reg_base, reg_base 111 drivers/clk/pistachio/clk.h unsigned long reg_base; reg_base 122 drivers/clk/pistachio/clk.h .reg_base = _reg, \ reg_base 133 drivers/clk/pistachio/clk.h .reg_base = _reg, \ reg_base 59 drivers/clk/rockchip/clk-cpu.c void __iomem *reg_base; reg_base 91 drivers/clk/rockchip/clk-cpu.c u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); reg_base 116 drivers/clk/rockchip/clk-cpu.c writel(clksel->val, cpuclk->reg_base + clksel->reg); reg_base 170 drivers/clk/rockchip/clk-cpu.c cpuclk->reg_base + reg_data->core_reg); reg_base 176 drivers/clk/rockchip/clk-cpu.c cpuclk->reg_base + reg_data->core_reg); reg_base 214 drivers/clk/rockchip/clk-cpu.c cpuclk->reg_base + reg_data->core_reg); reg_base 250 drivers/clk/rockchip/clk-cpu.c int nrates, void __iomem *reg_base, spinlock_t *lock) reg_base 279 drivers/clk/rockchip/clk-cpu.c cpuclk->reg_base = reg_base; reg_base 17 drivers/clk/rockchip/clk-ddr.c void __iomem *reg_base; reg_base 76 drivers/clk/rockchip/clk-ddr.c val = readl(ddrclk->reg_base + reg_base 95 drivers/clk/rockchip/clk-ddr.c int ddr_flag, void __iomem *reg_base, reg_base 123 drivers/clk/rockchip/clk-ddr.c ddrclk->reg_base = reg_base; reg_base 33 drivers/clk/rockchip/clk-pll.c void __iomem *reg_base; reg_base 133 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); reg_base 139 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); reg_base 147 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); reg_base 207 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(0)); reg_base 215 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); reg_base 218 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); reg_base 221 drivers/clk/rockchip/clk-pll.c writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); reg_base 262 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); reg_base 274 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); reg_base 280 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); reg_base 372 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); reg_base 378 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); reg_base 382 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); reg_base 395 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); reg_base 435 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); reg_base 442 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(0)); reg_base 446 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(1)); reg_base 449 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(2)); reg_base 453 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); reg_base 495 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); reg_base 507 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); reg_base 513 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); reg_base 592 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); reg_base 608 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); reg_base 612 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); reg_base 620 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); reg_base 624 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); reg_base 682 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(0)); reg_base 690 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(1)); reg_base 693 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); reg_base 696 drivers/clk/rockchip/clk-pll.c writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); reg_base 700 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); reg_base 741 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); reg_base 753 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); reg_base 759 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); reg_base 862 drivers/clk/rockchip/clk-pll.c pll_mux->reg = ctx->reg_base + mode_offset; reg_base 949 drivers/clk/rockchip/clk-pll.c pll->reg_base = ctx->reg_base + con_offset; reg_base 962 drivers/clk/rockchip/clk-px30.c void __iomem *reg_base; reg_base 964 drivers/clk/rockchip/clk-px30.c reg_base = of_iomap(np, 0); reg_base 965 drivers/clk/rockchip/clk-px30.c if (!reg_base) { reg_base 970 drivers/clk/rockchip/clk-px30.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 973 drivers/clk/rockchip/clk-px30.c iounmap(reg_base); reg_base 988 drivers/clk/rockchip/clk-px30.c rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), reg_base 1000 drivers/clk/rockchip/clk-px30.c void __iomem *reg_base; reg_base 1002 drivers/clk/rockchip/clk-px30.c reg_base = of_iomap(np, 0); reg_base 1003 drivers/clk/rockchip/clk-px30.c if (!reg_base) { reg_base 1008 drivers/clk/rockchip/clk-px30.c ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); reg_base 437 drivers/clk/rockchip/clk-rk3036.c void __iomem *reg_base; reg_base 440 drivers/clk/rockchip/clk-rk3036.c reg_base = of_iomap(np, 0); reg_base 441 drivers/clk/rockchip/clk-rk3036.c if (!reg_base) { reg_base 451 drivers/clk/rockchip/clk-rk3036.c reg_base + RK2928_CLKSEL_CON(13)); reg_base 453 drivers/clk/rockchip/clk-rk3036.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 456 drivers/clk/rockchip/clk-rk3036.c iounmap(reg_base); reg_base 478 drivers/clk/rockchip/clk-rk3036.c rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), reg_base 579 drivers/clk/rockchip/clk-rk3128.c void __iomem *reg_base; reg_base 581 drivers/clk/rockchip/clk-rk3128.c reg_base = of_iomap(np, 0); reg_base 582 drivers/clk/rockchip/clk-rk3128.c if (!reg_base) { reg_base 587 drivers/clk/rockchip/clk-rk3128.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 590 drivers/clk/rockchip/clk-rk3128.c iounmap(reg_base); reg_base 605 drivers/clk/rockchip/clk-rk3128.c rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), reg_base 759 drivers/clk/rockchip/clk-rk3188.c void __iomem *reg_base; reg_base 761 drivers/clk/rockchip/clk-rk3188.c reg_base = of_iomap(np, 0); reg_base 762 drivers/clk/rockchip/clk-rk3188.c if (!reg_base) { reg_base 767 drivers/clk/rockchip/clk-rk3188.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 770 drivers/clk/rockchip/clk-rk3188.c iounmap(reg_base); reg_base 777 drivers/clk/rockchip/clk-rk3188.c rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), reg_base 685 drivers/clk/rockchip/clk-rk3228.c void __iomem *reg_base; reg_base 687 drivers/clk/rockchip/clk-rk3228.c reg_base = of_iomap(np, 0); reg_base 688 drivers/clk/rockchip/clk-rk3228.c if (!reg_base) { reg_base 693 drivers/clk/rockchip/clk-rk3228.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 696 drivers/clk/rockchip/clk-rk3228.c iounmap(reg_base); reg_base 713 drivers/clk/rockchip/clk-rk3228.c rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), reg_base 919 drivers/clk/rockchip/clk-rk3308.c void __iomem *reg_base; reg_base 921 drivers/clk/rockchip/clk-rk3308.c reg_base = of_iomap(np, 0); reg_base 922 drivers/clk/rockchip/clk-rk3308.c if (!reg_base) { reg_base 927 drivers/clk/rockchip/clk-rk3308.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 930 drivers/clk/rockchip/clk-rk3308.c iounmap(reg_base); reg_base 947 drivers/clk/rockchip/clk-rk3308.c rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0), reg_base 883 drivers/clk/rockchip/clk-rk3328.c void __iomem *reg_base; reg_base 885 drivers/clk/rockchip/clk-rk3328.c reg_base = of_iomap(np, 0); reg_base 886 drivers/clk/rockchip/clk-rk3328.c if (!reg_base) { reg_base 891 drivers/clk/rockchip/clk-rk3328.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 894 drivers/clk/rockchip/clk-rk3328.c iounmap(reg_base); reg_base 911 drivers/clk/rockchip/clk-rk3328.c rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0), reg_base 867 drivers/clk/rockchip/clk-rk3368.c void __iomem *reg_base; reg_base 869 drivers/clk/rockchip/clk-rk3368.c reg_base = of_iomap(np, 0); reg_base 870 drivers/clk/rockchip/clk-rk3368.c if (!reg_base) { reg_base 875 drivers/clk/rockchip/clk-rk3368.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 878 drivers/clk/rockchip/clk-rk3368.c iounmap(reg_base); reg_base 900 drivers/clk/rockchip/clk-rk3368.c rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0), reg_base 1527 drivers/clk/rockchip/clk-rk3399.c void __iomem *reg_base; reg_base 1529 drivers/clk/rockchip/clk-rk3399.c reg_base = of_iomap(np, 0); reg_base 1530 drivers/clk/rockchip/clk-rk3399.c if (!reg_base) { reg_base 1535 drivers/clk/rockchip/clk-rk3399.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 1538 drivers/clk/rockchip/clk-rk3399.c iounmap(reg_base); reg_base 1561 drivers/clk/rockchip/clk-rk3399.c rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), reg_base 1573 drivers/clk/rockchip/clk-rk3399.c void __iomem *reg_base; reg_base 1575 drivers/clk/rockchip/clk-rk3399.c reg_base = of_iomap(np, 0); reg_base 1576 drivers/clk/rockchip/clk-rk3399.c if (!reg_base) { reg_base 1581 drivers/clk/rockchip/clk-rk3399.c ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); reg_base 1584 drivers/clk/rockchip/clk-rk3399.c iounmap(reg_base); reg_base 1597 drivers/clk/rockchip/clk-rk3399.c rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), reg_base 787 drivers/clk/rockchip/clk-rv1108.c void __iomem *reg_base; reg_base 789 drivers/clk/rockchip/clk-rv1108.c reg_base = of_iomap(np, 0); reg_base 790 drivers/clk/rockchip/clk-rv1108.c if (!reg_base) { reg_base 795 drivers/clk/rockchip/clk-rv1108.c ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 798 drivers/clk/rockchip/clk-rv1108.c iounmap(reg_base); reg_base 815 drivers/clk/rockchip/clk-rv1108.c rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), reg_base 382 drivers/clk/rockchip/clk.c ctx->reg_base = base; reg_base 454 drivers/clk/rockchip/clk.c flags, ctx->reg_base + list->muxdiv_offset, reg_base 470 drivers/clk/rockchip/clk.c ctx->reg_base + list->muxdiv_offset, reg_base 477 drivers/clk/rockchip/clk.c ctx->reg_base + list->muxdiv_offset, reg_base 484 drivers/clk/rockchip/clk.c ctx->reg_base, list->muxdiv_offset, reg_base 493 drivers/clk/rockchip/clk.c ctx->reg_base, list->muxdiv_offset, reg_base 505 drivers/clk/rockchip/clk.c ctx->reg_base + list->gate_offset, reg_base 511 drivers/clk/rockchip/clk.c ctx->reg_base, list->muxdiv_offset, reg_base 523 drivers/clk/rockchip/clk.c ctx->reg_base + list->muxdiv_offset, reg_base 531 drivers/clk/rockchip/clk.c ctx->reg_base + list->muxdiv_offset, reg_base 537 drivers/clk/rockchip/clk.c list->num_parents, ctx->reg_base, reg_base 549 drivers/clk/rockchip/clk.c ctx->reg_base, &ctx->lock); reg_base 582 drivers/clk/rockchip/clk.c ctx->reg_base, &ctx->lock); reg_base 631 drivers/clk/rockchip/clk.c rst_base = ctx->reg_base; reg_base 237 drivers/clk/rockchip/clk.h void __iomem *reg_base; reg_base 355 drivers/clk/rockchip/clk.h int nrates, void __iomem *reg_base, spinlock_t *lock); reg_base 372 drivers/clk/rockchip/clk.h int ddr_flags, void __iomem *reg_base, reg_base 15 drivers/clk/rockchip/softrst.c void __iomem *reg_base; reg_base 33 drivers/clk/rockchip/softrst.c softrst->reg_base + (bank * 4)); reg_base 40 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); reg_base 41 drivers/clk/rockchip/softrst.c writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); reg_base 59 drivers/clk/rockchip/softrst.c writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); reg_base 66 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); reg_base 67 drivers/clk/rockchip/softrst.c writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); reg_base 93 drivers/clk/rockchip/softrst.c softrst->reg_base = base; reg_base 425 drivers/clk/samsung/clk-cpu.c cpuclk->ctrl_base = ctx->reg_base + offset; reg_base 22 drivers/clk/samsung/clk-exynos-audss.c static void __iomem *reg_base; reg_base 47 drivers/clk/samsung/clk-exynos-audss.c reg_save[i][1] = readl(reg_base + reg_save[i][0]); reg_base 57 drivers/clk/samsung/clk-exynos-audss.c writel(reg_save[i][1], reg_base + reg_save[i][0]); reg_base 141 drivers/clk/samsung/clk-exynos-audss.c reg_base = devm_ioremap_resource(dev, res); reg_base 142 drivers/clk/samsung/clk-exynos-audss.c if (IS_ERR(reg_base)) reg_base 143 drivers/clk/samsung/clk-exynos-audss.c return PTR_ERR(reg_base); reg_base 189 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); reg_base 200 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); reg_base 204 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); reg_base 208 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); reg_base 211 drivers/clk/samsung/clk-exynos-audss.c "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, reg_base 216 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 0, 0, &lock); reg_base 220 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 2, 0, &lock); reg_base 224 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 3, 0, &lock); reg_base 228 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 4, 0, &lock); reg_base 235 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 5, 0, &lock); reg_base 240 drivers/clk/samsung/clk-exynos-audss.c reg_base + ASS_CLK_GATE, 9, 0, &lock); reg_base 751 drivers/clk/samsung/clk-exynos3250.c static void __init exynos3_core_down_clock(void __iomem *reg_base) reg_base 763 drivers/clk/samsung/clk-exynos3250.c __raw_writel(tmp, reg_base + PWR_CTRL1); reg_base 769 drivers/clk/samsung/clk-exynos3250.c __raw_writel(0x0, reg_base + PWR_CTRL2); reg_base 821 drivers/clk/samsung/clk-exynos3250.c exynos3_core_down_clock(ctx->reg_base); reg_base 150 drivers/clk/samsung/clk-exynos4.c static void __iomem *reg_base; reg_base 1184 drivers/clk/samsung/clk-exynos4.c writel_relaxed(tmp, reg_base + PWR_CTRL1); reg_base 1189 drivers/clk/samsung/clk-exynos4.c writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); reg_base 1238 drivers/clk/samsung/clk-exynos4.c reg_base = of_iomap(np, 0); reg_base 1239 drivers/clk/samsung/clk-exynos4.c if (!reg_base) reg_base 1242 drivers/clk/samsung/clk-exynos4.c ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 1266 drivers/clk/samsung/clk-exynos4.c ARRAY_SIZE(exynos4210_plls), reg_base); reg_base 1278 drivers/clk/samsung/clk-exynos4.c ARRAY_SIZE(exynos4x12_plls), reg_base); reg_base 1328 drivers/clk/samsung/clk-exynos4.c samsung_clk_extended_sleep_init(reg_base, reg_base 1332 drivers/clk/samsung/clk-exynos4.c samsung_clk_extended_sleep_init(reg_base, reg_base 1336 drivers/clk/samsung/clk-exynos4.c samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, reg_base 94 drivers/clk/samsung/clk-exynos4412-isp.c samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, reg_base 103 drivers/clk/samsung/clk-exynos4412-isp.c samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, reg_base 114 drivers/clk/samsung/clk-exynos4412-isp.c void __iomem *reg_base; reg_base 117 drivers/clk/samsung/clk-exynos4412-isp.c reg_base = devm_ioremap_resource(dev, res); reg_base 118 drivers/clk/samsung/clk-exynos4412-isp.c if (IS_ERR(reg_base)) { reg_base 120 drivers/clk/samsung/clk-exynos4412-isp.c return PTR_ERR(reg_base); reg_base 128 drivers/clk/samsung/clk-exynos4412-isp.c ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS); reg_base 68 drivers/clk/samsung/clk-exynos5-subcmu.c exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs, reg_base 79 drivers/clk/samsung/clk-exynos5-subcmu.c exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs, reg_base 92 drivers/clk/samsung/clk-exynos5-subcmu.c exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs, reg_base 109 drivers/clk/samsung/clk-exynos5250.c static void __iomem *reg_base; reg_base 787 drivers/clk/samsung/clk-exynos5250.c reg_base = of_iomap(np, 0); reg_base 788 drivers/clk/samsung/clk-exynos5250.c if (!reg_base) reg_base 794 drivers/clk/samsung/clk-exynos5250.c ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 812 drivers/clk/samsung/clk-exynos5250.c reg_base); reg_base 836 drivers/clk/samsung/clk-exynos5250.c __raw_writel(tmp, reg_base + PWR_CTRL1); reg_base 846 drivers/clk/samsung/clk-exynos5250.c __raw_writel(tmp, reg_base + PWR_CTRL2); reg_base 848 drivers/clk/samsung/clk-exynos5250.c samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, reg_base 155 drivers/clk/samsung/clk-exynos5420.c static void __iomem *reg_base; reg_base 1548 drivers/clk/samsung/clk-exynos5420.c reg_base = of_iomap(np, 0); reg_base 1549 drivers/clk/samsung/clk-exynos5420.c if (!reg_base) reg_base 1557 drivers/clk/samsung/clk-exynos5420.c ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); reg_base 1575 drivers/clk/samsung/clk-exynos5420.c reg_base); reg_base 1619 drivers/clk/samsung/clk-exynos5420.c samsung_clk_extended_sleep_init(reg_base, reg_base 1624 drivers/clk/samsung/clk-exynos5420.c samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, reg_base 3679 drivers/clk/samsung/clk-exynos5433.c void __iomem *reg_base; reg_base 3682 drivers/clk/samsung/clk-exynos5433.c reg_base = of_iomap(np, 0); reg_base 3683 drivers/clk/samsung/clk-exynos5433.c if (!reg_base) { reg_base 3688 drivers/clk/samsung/clk-exynos5433.c ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); reg_base 3695 drivers/clk/samsung/clk-exynos5433.c ARRAY_SIZE(apollo_pll_clks), reg_base); reg_base 3708 drivers/clk/samsung/clk-exynos5433.c samsung_clk_sleep_init(reg_base, apollo_clk_regs, reg_base 3933 drivers/clk/samsung/clk-exynos5433.c void __iomem *reg_base; reg_base 3936 drivers/clk/samsung/clk-exynos5433.c reg_base = of_iomap(np, 0); reg_base 3937 drivers/clk/samsung/clk-exynos5433.c if (!reg_base) { reg_base 3942 drivers/clk/samsung/clk-exynos5433.c ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); reg_base 3949 drivers/clk/samsung/clk-exynos5433.c ARRAY_SIZE(atlas_pll_clks), reg_base); reg_base 3962 drivers/clk/samsung/clk-exynos5433.c samsung_clk_sleep_init(reg_base, atlas_clk_regs, reg_base 5517 drivers/clk/samsung/clk-exynos5433.c samsung_clk_save(data->ctx.reg_base, data->clk_save, reg_base 5524 drivers/clk/samsung/clk-exynos5433.c samsung_clk_restore(data->ctx.reg_base, data->clk_suspend, reg_base 5545 drivers/clk/samsung/clk-exynos5433.c samsung_clk_restore(data->ctx.reg_base, data->clk_save, reg_base 5561 drivers/clk/samsung/clk-exynos5433.c void __iomem *reg_base; reg_base 5574 drivers/clk/samsung/clk-exynos5433.c reg_base = devm_ioremap_resource(dev, res); reg_base 5575 drivers/clk/samsung/clk-exynos5433.c if (IS_ERR(reg_base)) reg_base 5576 drivers/clk/samsung/clk-exynos5433.c return PTR_ERR(reg_base); reg_base 5582 drivers/clk/samsung/clk-exynos5433.c ctx->reg_base = reg_base; reg_base 5633 drivers/clk/samsung/clk-exynos5433.c reg_base); reg_base 37 drivers/clk/samsung/clk-s3c2410.c static void __iomem *reg_base; reg_base 325 drivers/clk/samsung/clk-s3c2410.c reg_base = base; reg_base 328 drivers/clk/samsung/clk-s3c2410.c reg_base = of_iomap(np, 0); reg_base 329 drivers/clk/samsung/clk-s3c2410.c if (!reg_base) reg_base 333 drivers/clk/samsung/clk-s3c2410.c ctx = samsung_clk_init(np, reg_base, NR_CLKS); reg_base 347 drivers/clk/samsung/clk-s3c2410.c ARRAY_SIZE(s3c2410_plls), reg_base); reg_base 363 drivers/clk/samsung/clk-s3c2410.c ARRAY_SIZE(s3c244x_common_plls), reg_base); reg_base 421 drivers/clk/samsung/clk-s3c2410.c samsung_clk_sleep_init(reg_base, s3c2410_clk_regs, reg_base 27 drivers/clk/samsung/clk-s3c2412.c static void __iomem *reg_base; reg_base 170 drivers/clk/samsung/clk-s3c2412.c __raw_writel(0x00, reg_base + CLKSRC); reg_base 171 drivers/clk/samsung/clk-s3c2412.c __raw_writel(0x533C2412, reg_base + SWRST); reg_base 210 drivers/clk/samsung/clk-s3c2412.c reg_base = base; reg_base 213 drivers/clk/samsung/clk-s3c2412.c reg_base = of_iomap(np, 0); reg_base 214 drivers/clk/samsung/clk-s3c2412.c if (!reg_base) reg_base 218 drivers/clk/samsung/clk-s3c2412.c ctx = samsung_clk_init(np, reg_base, NR_CLKS); reg_base 226 drivers/clk/samsung/clk-s3c2412.c reg_base); reg_base 239 drivers/clk/samsung/clk-s3c2412.c samsung_clk_sleep_init(reg_base, s3c2412_clk_regs, reg_base 41 drivers/clk/samsung/clk-s3c2443.c static void __iomem *reg_base; reg_base 313 drivers/clk/samsung/clk-s3c2443.c __raw_writel(0x533c2443, reg_base + SWRST); reg_base 347 drivers/clk/samsung/clk-s3c2443.c reg_base = base; reg_base 350 drivers/clk/samsung/clk-s3c2443.c reg_base = of_iomap(np, 0); reg_base 351 drivers/clk/samsung/clk-s3c2443.c if (!reg_base) reg_base 355 drivers/clk/samsung/clk-s3c2443.c ctx = samsung_clk_init(np, reg_base, NR_CLKS); reg_base 364 drivers/clk/samsung/clk-s3c2443.c ARRAY_SIZE(s3c2416_pll_clks), reg_base); reg_base 367 drivers/clk/samsung/clk-s3c2443.c ARRAY_SIZE(s3c2443_pll_clks), reg_base); reg_base 411 drivers/clk/samsung/clk-s3c2443.c samsung_clk_sleep_init(reg_base, s3c2443_clk_regs, reg_base 55 drivers/clk/samsung/clk-s3c64xx.c static void __iomem *reg_base; reg_base 397 drivers/clk/samsung/clk-s3c64xx.c reg_base = base; reg_base 401 drivers/clk/samsung/clk-s3c64xx.c reg_base = of_iomap(np, 0); reg_base 402 drivers/clk/samsung/clk-s3c64xx.c if (!reg_base) reg_base 406 drivers/clk/samsung/clk-s3c64xx.c ctx = samsung_clk_init(np, reg_base, NR_CLKS); reg_base 414 drivers/clk/samsung/clk-s3c64xx.c ARRAY_SIZE(s3c64xx_pll_clks), reg_base); reg_base 450 drivers/clk/samsung/clk-s3c64xx.c samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs, reg_base 453 drivers/clk/samsung/clk-s3c64xx.c samsung_clk_sleep_init(reg_base, s3c6410_clk_regs, reg_base 24 drivers/clk/samsung/clk-s5pv210-audss.c static void __iomem *reg_base; reg_base 43 drivers/clk/samsung/clk-s5pv210-audss.c reg_save[i][1] = readl(reg_base + reg_save[i][0]); reg_base 53 drivers/clk/samsung/clk-s5pv210-audss.c writel(reg_save[i][1], reg_base + reg_save[i][0]); reg_base 74 drivers/clk/samsung/clk-s5pv210-audss.c reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 75 drivers/clk/samsung/clk-s5pv210-audss.c if (IS_ERR(reg_base)) { reg_base 77 drivers/clk/samsung/clk-s5pv210-audss.c return PTR_ERR(reg_base); reg_base 120 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); reg_base 131 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); reg_base 135 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); reg_base 138 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); reg_base 142 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 6, 0, &lock); reg_base 148 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 5, 0, &lock); reg_base 151 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 4, 0, &lock); reg_base 154 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 3, 0, &lock); reg_base 157 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 2, 0, &lock); reg_base 160 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 1, 0, &lock); reg_base 163 drivers/clk/samsung/clk-s5pv210-audss.c reg_base + ASS_CLK_GATE, 0, 0, &lock); reg_base 80 drivers/clk/samsung/clk-s5pv210.c static void __iomem *reg_base; reg_base 745 drivers/clk/samsung/clk-s5pv210.c ctx = samsung_clk_init(np, reg_base, NR_CLKS); reg_base 754 drivers/clk/samsung/clk-s5pv210.c ARRAY_SIZE(s5p6442_pll_clks), reg_base); reg_base 765 drivers/clk/samsung/clk-s5pv210.c ARRAY_SIZE(s5pv210_pll_clks), reg_base); reg_base 784 drivers/clk/samsung/clk-s5pv210.c samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, reg_base 798 drivers/clk/samsung/clk-s5pv210.c reg_base = of_iomap(np, 0); reg_base 799 drivers/clk/samsung/clk-s5pv210.c if (!reg_base) reg_base 808 drivers/clk/samsung/clk-s5pv210.c reg_base = of_iomap(np, 0); reg_base 809 drivers/clk/samsung/clk-s5pv210.c if (!reg_base) reg_base 71 drivers/clk/samsung/clk.c ctx->reg_base = base; reg_base 187 drivers/clk/samsung/clk.c ctx->reg_base + list->offset, reg_base 211 drivers/clk/samsung/clk.c ctx->reg_base + list->offset, reg_base 217 drivers/clk/samsung/clk.c ctx->reg_base + list->offset, list->shift, reg_base 239 drivers/clk/samsung/clk.c list->flags, ctx->reg_base + list->offset, reg_base 292 drivers/clk/samsung/clk.c samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, reg_base 294 drivers/clk/samsung/clk.c samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend, reg_base 305 drivers/clk/samsung/clk.c samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump, reg_base 314 drivers/clk/samsung/clk.c void samsung_clk_extended_sleep_init(void __iomem *reg_base, reg_base 334 drivers/clk/samsung/clk.c reg_cache->reg_base = reg_base; reg_base 350 drivers/clk/samsung/clk.c void __iomem *reg_base; reg_base 353 drivers/clk/samsung/clk.c reg_base = of_iomap(np, 0); reg_base 354 drivers/clk/samsung/clk.c if (!reg_base) { reg_base 359 drivers/clk/samsung/clk.c ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); reg_base 367 drivers/clk/samsung/clk.c reg_base); reg_base 383 drivers/clk/samsung/clk.c samsung_clk_extended_sleep_init(reg_base, reg_base 23 drivers/clk/samsung/clk.h void __iomem *reg_base; reg_base 276 drivers/clk/samsung/clk.h void __iomem *reg_base; reg_base 361 drivers/clk/samsung/clk.h extern void samsung_clk_extended_sleep_init(void __iomem *reg_base, reg_base 367 drivers/clk/samsung/clk.h static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base, reg_base 373 drivers/clk/samsung/clk.h #define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \ reg_base 374 drivers/clk/samsung/clk.h samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0) reg_base 565 drivers/clk/zte/clk-zx296718.c void __iomem *reg_base; reg_base 569 drivers/clk/zte/clk-zx296718.c reg_base = of_iomap(np, 0); reg_base 570 drivers/clk/zte/clk-zx296718.c if (!reg_base) { reg_base 576 drivers/clk/zte/clk-zx296718.c zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base; reg_base 599 drivers/clk/zte/clk-zx296718.c top_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg_base 611 drivers/clk/zte/clk-zx296718.c top_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg_base 623 drivers/clk/zte/clk-zx296718.c top_div_clk[i].div.reg += (uintptr_t)reg_base; reg_base 751 drivers/clk/zte/clk-zx296718.c void __iomem *reg_base; reg_base 755 drivers/clk/zte/clk-zx296718.c reg_base = of_iomap(np, 0); reg_base 756 drivers/clk/zte/clk-zx296718.c if (!reg_base) { reg_base 766 drivers/clk/zte/clk-zx296718.c lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg_base 778 drivers/clk/zte/clk-zx296718.c lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg_base 790 drivers/clk/zte/clk-zx296718.c lsp0_div_clk[i].div.reg += (uintptr_t)reg_base; reg_base 857 drivers/clk/zte/clk-zx296718.c void __iomem *reg_base; reg_base 861 drivers/clk/zte/clk-zx296718.c reg_base = of_iomap(np, 0); reg_base 862 drivers/clk/zte/clk-zx296718.c if (!reg_base) { reg_base 872 drivers/clk/zte/clk-zx296718.c lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg_base 884 drivers/clk/zte/clk-zx296718.c lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg_base 896 drivers/clk/zte/clk-zx296718.c lsp1_div_clk[i].div.reg += (uintptr_t)reg_base; reg_base 972 drivers/clk/zte/clk-zx296718.c void __iomem *reg_base; reg_base 976 drivers/clk/zte/clk-zx296718.c reg_base = of_iomap(np, 0); reg_base 977 drivers/clk/zte/clk-zx296718.c if (!reg_base) { reg_base 987 drivers/clk/zte/clk-zx296718.c audio_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg_base 999 drivers/clk/zte/clk-zx296718.c audio_adiv_clk[i].reg_base += (uintptr_t)reg_base; reg_base 1011 drivers/clk/zte/clk-zx296718.c audio_div_clk[i].div.reg += (uintptr_t)reg_base; reg_base 1023 drivers/clk/zte/clk-zx296718.c audio_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg_base 47 drivers/clk/zte/clk.c hw_cfg0 = readl_relaxed(zx_pll->reg_base); reg_base 48 drivers/clk/zte/clk.c hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); reg_base 100 drivers/clk/zte/clk.c writel_relaxed(config->cfg0, zx_pll->reg_base); reg_base 101 drivers/clk/zte/clk.c writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); reg_base 115 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg_base 116 drivers/clk/zte/clk.c writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); reg_base 118 drivers/clk/zte/clk.c return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, reg_base 130 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg_base 131 drivers/clk/zte/clk.c writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); reg_base 139 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg_base 155 drivers/clk/zte/clk.c unsigned long flags, void __iomem *reg_base, reg_base 173 drivers/clk/zte/clk.c zx_pll->reg_base = reg_base; reg_base 237 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg_base 260 drivers/clk/zte/clk.c writel_relaxed(reg, zx_audio->reg_base); reg_base 271 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg_base 272 drivers/clk/zte/clk.c writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base); reg_base 281 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg_base 282 drivers/clk/zte/clk.c writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base); reg_base 296 drivers/clk/zte/clk.c void __iomem *reg_base) reg_base 312 drivers/clk/zte/clk.c zx_audio->reg_base = reg_base; reg_base 398 drivers/clk/zte/clk.c reg_frac = readl_relaxed(zx_audio_div->reg_base); reg_base 399 drivers/clk/zte/clk.c reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4); reg_base 426 drivers/clk/zte/clk.c writel_relaxed(divt.frac_reg, zx_audio_div->reg_base); reg_base 428 drivers/clk/zte/clk.c val = readl_relaxed(zx_audio_div->reg_base + 0x4); reg_base 431 drivers/clk/zte/clk.c writel_relaxed(val, zx_audio_div->reg_base + 0x4); reg_base 435 drivers/clk/zte/clk.c val = readl_relaxed(zx_audio_div->reg_base + 0x4); reg_base 437 drivers/clk/zte/clk.c writel_relaxed(val, zx_audio_div->reg_base + 0x4); reg_base 22 drivers/clk/zte/clk.h void __iomem *reg_base; reg_base 39 drivers/clk/zte/clk.h .reg_base = (void __iomem *) _reg, \ reg_base 141 drivers/clk/zte/clk.h void __iomem *reg_base; reg_base 149 drivers/clk/zte/clk.h .reg_base = (void __iomem *) _reg, \ reg_base 159 drivers/clk/zte/clk.h unsigned long flags, void __iomem *reg_base, reg_base 164 drivers/clk/zte/clk.h void __iomem *reg_base; reg_base 169 drivers/clk/zte/clk.h unsigned long flags, void __iomem *reg_base); reg_base 75 drivers/clocksource/exynos_mct.c static void __iomem *reg_base; reg_base 92 drivers/clocksource/exynos_mct.c writel_relaxed(value, reg_base + offset); reg_base 142 drivers/clocksource/exynos_mct.c if (readl_relaxed(reg_base + stat_addr) & mask) { reg_base 143 drivers/clocksource/exynos_mct.c writel_relaxed(mask, reg_base + stat_addr); reg_base 155 drivers/clocksource/exynos_mct.c reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); reg_base 173 drivers/clocksource/exynos_mct.c u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); reg_base 177 drivers/clocksource/exynos_mct.c lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); reg_base 178 drivers/clocksource/exynos_mct.c hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); reg_base 194 drivers/clocksource/exynos_mct.c return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); reg_base 254 drivers/clocksource/exynos_mct.c tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); reg_base 266 drivers/clocksource/exynos_mct.c tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); reg_base 358 drivers/clocksource/exynos_mct.c tmp = readl_relaxed(reg_base + offset); reg_base 380 drivers/clocksource/exynos_mct.c tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); reg_base 389 drivers/clocksource/exynos_mct.c if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) reg_base 516 drivers/clocksource/exynos_mct.c reg_base = base; reg_base 517 drivers/clocksource/exynos_mct.c if (!reg_base) reg_base 57 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); reg_base 68 drivers/clocksource/timer-tegra.c writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); reg_base 75 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); reg_base 77 drivers/clocksource/timer-tegra.c writel_relaxed(0, reg_base + TIMER_PTV); reg_base 84 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); reg_base 88 drivers/clocksource/timer-tegra.c reg_base + TIMER_PTV); reg_base 96 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); reg_base 98 drivers/clocksource/timer-tegra.c writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); reg_base 106 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(to_timer_of(evt)); reg_base 108 drivers/clocksource/timer-tegra.c writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); reg_base 196 drivers/clocksource/timer-tegra.c void __iomem *reg_base = timer_of_base(&suspend_rtc_to); reg_base 198 drivers/clocksource/timer-tegra.c u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); reg_base 199 drivers/clocksource/timer-tegra.c u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); reg_base 50 drivers/crypto/cavium/cpt/cptpf.h void __iomem *reg_base; /* Register start address */ reg_base 39 drivers/crypto/cavium/cpt/cptpf_main.c grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); reg_base 40 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), reg_base 43 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); reg_base 46 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, reg_base 55 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); reg_base 56 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), reg_base 72 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); reg_base 73 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), reg_base 86 drivers/crypto/cavium/cpt/cptpf_main.c pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); reg_base 87 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), reg_base 95 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); reg_base 101 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); reg_base 107 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); reg_base 120 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); reg_base 153 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, reg_base 348 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1); reg_base 355 drivers/crypto/cavium/cpt/cptpf_main.c pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0)); reg_base 364 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, reg_base 374 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, reg_base 387 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0); reg_base 391 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); reg_base 394 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, reg_base 402 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0); reg_base 425 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, reg_base 585 drivers/crypto/cavium/cpt/cptpf_main.c cpt->reg_base = pcim_iomap(pdev, 0, 0); reg_base 586 drivers/crypto/cavium/cpt/cptpf_main.c if (!cpt->reg_base) { reg_base 12 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), reg_base 14 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); reg_base 31 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); reg_base 41 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); reg_base 44 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); reg_base 54 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); reg_base 56 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); reg_base 77 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q)); reg_base 79 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u); reg_base 96 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0)); reg_base 97 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.data = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1)); reg_base 151 drivers/crypto/cavium/cpt/cptpf_mbox.c intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0)); reg_base 104 drivers/crypto/cavium/cpt/cptvf.h void __iomem *reg_base; /* Register start address */ reg_base 369 drivers/crypto/cavium/cpt/cptvf_main.c vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0)); reg_base 371 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u); reg_base 378 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, reg_base 381 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0), reg_base 389 drivers/crypto/cavium/cpt/cptvf_main.c vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0)); reg_base 391 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u); reg_base 398 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, reg_base 401 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), reg_base 409 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, reg_base 412 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), reg_base 420 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, reg_base 424 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), reg_base 432 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, reg_base 436 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), reg_base 444 drivers/crypto/cavium/cpt/cptvf_main.c vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base, reg_base 448 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ENA_W1S(0, 0), reg_base 456 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, reg_base 460 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), reg_base 468 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, reg_base 472 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), reg_base 480 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, reg_base 484 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, reg_base 492 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, reg_base 496 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), reg_base 504 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, reg_base 508 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), reg_base 514 drivers/crypto/cavium/cpt/cptvf_main.c return cpt_read_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0)); reg_base 572 drivers/crypto/cavium/cpt/cptvf_main.c vqx_done.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_DONE(0, 0)); reg_base 581 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dack_cnt.u = cpt_read_csr64(cptvf->reg_base, reg_base 584 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ACK(0, 0), reg_base 638 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_SADDR(0, 0), vqx_saddr.u); reg_base 703 drivers/crypto/cavium/cpt/cptvf_main.c cptvf->reg_base = pcim_iomap(pdev, 0, 0); reg_base 704 drivers/crypto/cavium/cpt/cptvf_main.c if (!cptvf->reg_base) { reg_base 11 drivers/crypto/cavium/cpt/cptvf_mbox.c cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0), reg_base 13 drivers/crypto/cavium/cpt/cptvf_mbox.c cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1), reg_base 26 drivers/crypto/cavium/cpt/cptvf_mbox.c mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0)); reg_base 27 drivers/crypto/cavium/cpt/cptvf_mbox.c mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1)); reg_base 161 drivers/crypto/cavium/zip/zip_device.c (zip_dev->reg_base + ZIP_QUEX_DOORBELL(queue))); reg_base 134 drivers/crypto/cavium/zip/zip_main.c cmd_ctl.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CMD_CTL); reg_base 136 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(cmd_ctl.u_reg64 & 0xFF, (zip->reg_base + ZIP_CMD_CTL)); reg_base 139 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_CMD_CTL)); reg_base 141 drivers/crypto/cavium/zip/zip_main.c constants.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CONSTANTS); reg_base 160 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_SBUF_CTL(q))); reg_base 163 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_CTL(q))); reg_base 192 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_SBUF_ADDR(q))); reg_base 195 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_ADDR(q))); reg_base 212 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(que_ena.u_reg64, (zip->reg_base + ZIP_QUE_ENA)); reg_base 215 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUE_ENA)); reg_base 222 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_MAP(q))); reg_base 225 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_MAP(q))); reg_base 231 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(que_pri.u_reg64, (zip->reg_base + ZIP_QUE_PRI)); reg_base 233 drivers/crypto/cavium/zip/zip_main.c zip_msg("QUE_PRI %016llx", zip_reg_read(zip->reg_base + ZIP_QUE_PRI)); reg_base 279 drivers/crypto/cavium/zip/zip_main.c zip->reg_base = pci_ioremap_bar(pdev, PCI_CFG_ZIP_PF_BAR0); reg_base 280 drivers/crypto/cavium/zip/zip_main.c if (!zip->reg_base) { reg_base 294 drivers/crypto/cavium/zip/zip_main.c if (zip->reg_base) reg_base 295 drivers/crypto/cavium/zip/zip_main.c iounmap(zip->reg_base); reg_base 320 drivers/crypto/cavium/zip/zip_main.c if (zip->reg_base) { reg_base 323 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(cmd_ctl.u_reg64, (zip->reg_base + ZIP_CMD_CTL)); reg_base 324 drivers/crypto/cavium/zip/zip_main.c iounmap(zip->reg_base); reg_base 482 drivers/crypto/cavium/zip/zip_main.c val = zip_reg_read((zip->reg_base + reg_base 576 drivers/crypto/cavium/zip/zip_main.c val = zip_reg_read((zip_dev[index]->reg_base + reg_base 100 drivers/crypto/cavium/zip/zip_main.h void __iomem *reg_base; reg_base 87 drivers/dma/ioat/dma.c intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 93 drivers/dma/ioat/dma.c writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 97 drivers/dma/ioat/dma.c attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); reg_base 104 drivers/dma/ioat/dma.c writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 164 drivers/dma/ioat/dma.c ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); reg_base 437 drivers/dma/ioat/dma.c writew(drsctl, ioat_chan->reg_base + IOAT_CHAN_DRSCTL_OFFSET); reg_base 651 drivers/dma/ioat/dma.c ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET); reg_base 666 drivers/dma/ioat/dma.c u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 685 drivers/dma/ioat/dma.c writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); reg_base 694 drivers/dma/ioat/dma.c ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); reg_base 696 drivers/dma/ioat/dma.c ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); reg_base 776 drivers/dma/ioat/dma.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 852 drivers/dma/ioat/dma.c writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 884 drivers/dma/ioat/dma.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 931 drivers/dma/ioat/dma.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 991 drivers/dma/ioat/dma.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 992 drivers/dma/ioat/dma.c writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 1018 drivers/dma/ioat/dma.c ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000); reg_base 1019 drivers/dma/ioat/dma.c ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008); reg_base 1020 drivers/dma/ioat/dma.c ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800); reg_base 1027 drivers/dma/ioat/dma.c writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000); reg_base 1028 drivers/dma/ioat/dma.c writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008); reg_base 1029 drivers/dma/ioat/dma.c writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800); reg_base 26 drivers/dma/ioat/dma.h #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) reg_base 65 drivers/dma/ioat/dma.h void __iomem *reg_base; reg_base 91 drivers/dma/ioat/dma.h void __iomem *reg_base; reg_base 240 drivers/dma/ioat/dma.h return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); reg_base 250 drivers/dma/ioat/dma.h return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 258 drivers/dma/ioat/dma.h ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); reg_base 266 drivers/dma/ioat/dma.h ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); reg_base 274 drivers/dma/ioat/dma.h cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); reg_base 351 drivers/dma/ioat/dma.h ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); reg_base 353 drivers/dma/ioat/dma.h ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); reg_base 476 drivers/dma/ioat/init.c writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 481 drivers/dma/ioat/init.c writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 490 drivers/dma/ioat/init.c writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET); reg_base 578 drivers/dma/ioat/init.c dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET); reg_base 585 drivers/dma/ioat/init.c xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET); reg_base 632 drivers/dma/ioat/init.c ioat_chan->reg_base + IOAT_CHAN_LTR_SWSEL_OFFSET); reg_base 692 drivers/dma/ioat/init.c writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); reg_base 703 drivers/dma/ioat/init.c ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); reg_base 705 drivers/dma/ioat/init.c ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); reg_base 730 drivers/dma/ioat/init.c writel(lat_val, ioat_chan->reg_base + reg_base 736 drivers/dma/ioat/init.c writel(lat_val, ioat_chan->reg_base + reg_base 741 drivers/dma/ioat/init.c ioat_chan->reg_base + reg_base 756 drivers/dma/ioat/init.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 774 drivers/dma/ioat/init.c ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1)); reg_base 1079 drivers/dma/ioat/init.c errmask = readl(ioat_chan->reg_base + reg_base 1083 drivers/dma/ioat/init.c writel(errmask, ioat_chan->reg_base + reg_base 1108 drivers/dma/ioat/init.c ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET); reg_base 1183 drivers/dma/ioat/init.c ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); reg_base 1193 drivers/dma/ioat/init.c ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); reg_base 1208 drivers/dma/ioat/init.c ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET); reg_base 1260 drivers/dma/ioat/init.c chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 1261 drivers/dma/ioat/init.c writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); reg_base 1334 drivers/dma/ioat/init.c d->reg_base = iobase; reg_base 1374 drivers/dma/ioat/init.c device->version = readb(device->reg_base + IOAT_VER_OFFSET); reg_base 120 drivers/dma/mmp_tdma.c void __iomem *reg_base; reg_base 145 drivers/dma/mmp_tdma.c writel(phys, tdmac->reg_base + TDNDPR); reg_base 146 drivers/dma/mmp_tdma.c writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, reg_base 147 drivers/dma/mmp_tdma.c tdmac->reg_base + TDCR); reg_base 153 drivers/dma/mmp_tdma.c writel(TDIMR_COMP, tdmac->reg_base + TDIMR); reg_base 155 drivers/dma/mmp_tdma.c writel(0, tdmac->reg_base + TDIMR); reg_base 161 drivers/dma/mmp_tdma.c writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, reg_base 162 drivers/dma/mmp_tdma.c tdmac->reg_base + TDCR); reg_base 171 drivers/dma/mmp_tdma.c tdcr = readl(tdmac->reg_base + TDCR); reg_base 174 drivers/dma/mmp_tdma.c writel(tdcr, tdmac->reg_base + TDCR); reg_base 185 drivers/dma/mmp_tdma.c writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, reg_base 186 drivers/dma/mmp_tdma.c tdmac->reg_base + TDCR); reg_base 196 drivers/dma/mmp_tdma.c writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, reg_base 197 drivers/dma/mmp_tdma.c tdmac->reg_base + TDCR); reg_base 284 drivers/dma/mmp_tdma.c writel(tdcr, tdmac->reg_base + TDCR); reg_base 290 drivers/dma/mmp_tdma.c u32 reg = readl(tdmac->reg_base + TDISR); reg_base 295 drivers/dma/mmp_tdma.c writel(reg, tdmac->reg_base + TDISR); reg_base 307 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDSAR); reg_base 310 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDDAR); reg_base 575 drivers/dma/mmp_tdma.c tdmac->reg_base = tdev->base + idx * 4; reg_base 70 drivers/dma/uniphier-mdmac.c void __iomem *reg_base; reg_base 141 drivers/dma/uniphier-mdmac.c writel(BIT(mc->chan_id), mdev->reg_base + UNIPHIER_MDMAC_CMD); reg_base 165 drivers/dma/uniphier-mdmac.c mdev->reg_base + UNIPHIER_MDMAC_CMD); reg_base 371 drivers/dma/uniphier-mdmac.c mc->reg_ch_base = mdev->reg_base + UNIPHIER_MDMAC_CH_OFFSET + reg_base 402 drivers/dma/uniphier-mdmac.c mdev->reg_base = devm_ioremap_resource(dev, res); reg_base 403 drivers/dma/uniphier-mdmac.c if (IS_ERR(mdev->reg_base)) reg_base 404 drivers/dma/uniphier-mdmac.c return PTR_ERR(mdev->reg_base); reg_base 17 drivers/fpga/altera-pr-ip-core-plat.c void __iomem *reg_base; reg_base 23 drivers/fpga/altera-pr-ip-core-plat.c reg_base = devm_ioremap_resource(dev, res); reg_base 25 drivers/fpga/altera-pr-ip-core-plat.c if (IS_ERR(reg_base)) reg_base 26 drivers/fpga/altera-pr-ip-core-plat.c return PTR_ERR(reg_base); reg_base 28 drivers/fpga/altera-pr-ip-core-plat.c return alt_pr_register(dev, reg_base); reg_base 29 drivers/fpga/altera-pr-ip-core.c void __iomem *reg_base; reg_base 39 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); reg_base 90 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); reg_base 99 drivers/fpga/altera-pr-ip-core.c writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); reg_base 116 drivers/fpga/altera-pr-ip-core.c writel(buffer_32[i++], priv->reg_base); reg_base 123 drivers/fpga/altera-pr-ip-core.c writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); reg_base 126 drivers/fpga/altera-pr-ip-core.c writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); reg_base 129 drivers/fpga/altera-pr-ip-core.c writel(buffer_32[i++] & 0x000000ff, priv->reg_base); reg_base 176 drivers/fpga/altera-pr-ip-core.c int alt_pr_register(struct device *dev, void __iomem *reg_base) reg_base 186 drivers/fpga/altera-pr-ip-core.c priv->reg_base = reg_base; reg_base 188 drivers/fpga/altera-pr-ip-core.c val = readl(priv->reg_base + ALT_PR_CSR_OFST); reg_base 472 drivers/fpga/socfpga-a10.c void __iomem *reg_base; reg_base 483 drivers/fpga/socfpga-a10.c reg_base = devm_ioremap_resource(dev, res); reg_base 484 drivers/fpga/socfpga-a10.c if (IS_ERR(reg_base)) reg_base 485 drivers/fpga/socfpga-a10.c return PTR_ERR(reg_base); reg_base 494 drivers/fpga/socfpga-a10.c priv->regmap = devm_regmap_init_mmio(dev, reg_base, reg_base 27 drivers/gpio/gpio-amdpt.c void __iomem *reg_base; reg_base 40 drivers/gpio/gpio-amdpt.c using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); reg_base 48 drivers/gpio/gpio-amdpt.c writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); reg_base 63 drivers/gpio/gpio-amdpt.c using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); reg_base 65 drivers/gpio/gpio-amdpt.c writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); reg_base 89 drivers/gpio/gpio-amdpt.c pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 90 drivers/gpio/gpio-amdpt.c if (IS_ERR(pt_gpio->reg_base)) { reg_base 92 drivers/gpio/gpio-amdpt.c return PTR_ERR(pt_gpio->reg_base); reg_base 96 drivers/gpio/gpio-amdpt.c pt_gpio->reg_base + PT_INPUTDATA_REG, reg_base 97 drivers/gpio/gpio-amdpt.c pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, reg_base 98 drivers/gpio/gpio-amdpt.c pt_gpio->reg_base + PT_DIRECTION_REG, NULL, reg_base 121 drivers/gpio/gpio-amdpt.c writel(0, pt_gpio->reg_base + PT_SYNC_REG); reg_base 122 drivers/gpio/gpio-amdpt.c writel(0, pt_gpio->reg_base + PT_CLOCKRATE_REG); reg_base 68 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 84 drivers/gpio/gpio-bcm-kona.c static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, reg_base 87 drivers/gpio/gpio-bcm-kona.c writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); reg_base 88 drivers/gpio/gpio-bcm-kona.c writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); reg_base 100 drivers/gpio/gpio-bcm-kona.c val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); reg_base 102 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); reg_base 116 drivers/gpio/gpio-bcm-kona.c val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); reg_base 118 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); reg_base 126 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base = kona_gpio->reg_base; reg_base 129 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; reg_base 136 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 143 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 152 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_base 154 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); reg_base 163 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 170 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 179 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_base 205 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 210 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 213 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); reg_base 216 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); reg_base 227 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 234 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 237 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); reg_base 240 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); reg_base 243 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + reg_offset); reg_base 245 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + reg_offset); reg_base 266 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 271 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 293 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); reg_base 304 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); reg_base 341 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 349 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 352 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_STATUS(bank_id)); reg_base 354 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_STATUS(bank_id)); reg_base 362 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 370 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 373 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_MASK(bank_id)); reg_base 375 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_MASK(bank_id)); reg_base 384 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 392 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 395 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); reg_base 397 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); reg_base 406 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 413 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 438 drivers/gpio/gpio-bcm-kona.c val = readl(reg_base + GPIO_CONTROL(gpio)); reg_base 441 drivers/gpio/gpio-bcm-kona.c writel(val, reg_base + GPIO_CONTROL(gpio)); reg_base 450 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 463 drivers/gpio/gpio-bcm-kona.c reg_base = bank->kona_gpio->reg_base; reg_base 466 drivers/gpio/gpio-bcm-kona.c while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & reg_base 467 drivers/gpio/gpio-bcm-kona.c (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { reg_base 477 drivers/gpio/gpio-bcm-kona.c writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) | reg_base 478 drivers/gpio/gpio-bcm-kona.c BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); reg_base 552 drivers/gpio/gpio-bcm-kona.c void __iomem *reg_base; reg_base 555 drivers/gpio/gpio-bcm-kona.c reg_base = kona_gpio->reg_base; reg_base 559 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE); reg_base 560 drivers/gpio/gpio-bcm-kona.c writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); reg_base 561 drivers/gpio/gpio-bcm-kona.c writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); reg_base 563 drivers/gpio/gpio-bcm-kona.c bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE); reg_base 620 drivers/gpio/gpio-bcm-kona.c kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 621 drivers/gpio/gpio-bcm-kona.c if (IS_ERR(kona_gpio->reg_base)) { reg_base 622 drivers/gpio/gpio-bcm-kona.c ret = PTR_ERR(kona_gpio->reg_base); reg_base 58 drivers/gpio/gpio-brcmstb.c void __iomem *reg_base; reg_base 83 drivers/gpio/gpio-brcmstb.c void __iomem *reg_base = bank->parent_priv->reg_base; reg_base 85 drivers/gpio/gpio-brcmstb.c return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & reg_base 86 drivers/gpio/gpio-brcmstb.c bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); reg_base 118 drivers/gpio/gpio-brcmstb.c imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); reg_base 123 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); reg_base 163 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); reg_base 209 drivers/gpio/gpio-brcmstb.c iedge_config = bank->gc.read_reg(priv->reg_base + reg_base 211 drivers/gpio/gpio-brcmstb.c iedge_insensitive = bank->gc.read_reg(priv->reg_base + reg_base 213 drivers/gpio/gpio-brcmstb.c ilevel = bank->gc.read_reg(priv->reg_base + reg_base 216 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), reg_base 218 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), reg_base 220 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), reg_base 520 drivers/gpio/gpio-brcmstb.c bank->saved_regs[i] = gc->read_reg(priv->reg_base + reg_base 546 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_MASK(bank->id), reg_base 565 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), reg_base 610 drivers/gpio/gpio-brcmstb.c void __iomem *reg_base; reg_base 629 drivers/gpio/gpio-brcmstb.c reg_base = devm_ioremap_resource(dev, res); reg_base 630 drivers/gpio/gpio-brcmstb.c if (IS_ERR(reg_base)) reg_base 631 drivers/gpio/gpio-brcmstb.c return PTR_ERR(reg_base); reg_base 634 drivers/gpio/gpio-brcmstb.c priv->reg_base = reg_base; reg_base 699 drivers/gpio/gpio-brcmstb.c reg_base + GIO_DATA(bank->id), reg_base 701 drivers/gpio/gpio-brcmstb.c reg_base + GIO_IODIR(bank->id), flags); reg_base 727 drivers/gpio/gpio-brcmstb.c gc->write_reg(reg_base + GIO_MASK(bank->id), 0); reg_base 132 drivers/gpio/gpio-dwapb.c void __iomem *reg_base = gpio->regs; reg_base 134 drivers/gpio/gpio-dwapb.c return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); reg_base 141 drivers/gpio/gpio-dwapb.c void __iomem *reg_base = gpio->regs; reg_base 143 drivers/gpio/gpio-dwapb.c gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); reg_base 418 drivers/gpio/gpio-dwapb.c irq_gc->reg_base = gpio->regs; reg_base 62 drivers/gpio/gpio-intel-mid.c void __iomem *reg_base; reg_base 74 drivers/gpio/gpio-intel-mid.c return priv->reg_base + reg_type * nreg * 4 + reg * 4; reg_base 84 drivers/gpio/gpio-intel-mid.c return priv->reg_base + reg_type * nreg * 4 + reg * 4; reg_base 361 drivers/gpio/gpio-intel-mid.c priv->reg_base = pcim_iomap_table(pdev)[0]; reg_base 165 drivers/gpio/gpio-lpc32xx.c void __iomem *reg_base; reg_base 170 drivers/gpio/gpio-lpc32xx.c return __raw_readl(group->reg_base + offset); reg_base 175 drivers/gpio/gpio-lpc32xx.c __raw_writel(val, group->reg_base + offset); reg_base 508 drivers/gpio/gpio-lpc32xx.c void __iomem *reg_base; reg_base 510 drivers/gpio/gpio-lpc32xx.c reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 511 drivers/gpio/gpio-lpc32xx.c if (IS_ERR(reg_base)) reg_base 512 drivers/gpio/gpio-lpc32xx.c return PTR_ERR(reg_base); reg_base 519 drivers/gpio/gpio-lpc32xx.c lpc32xx_gpiochip[i].reg_base = reg_base; reg_base 51 drivers/gpio/gpio-lynxpoint.c unsigned long reg_base; reg_base 96 drivers/gpio/gpio-lynxpoint.c return lg->reg_base + reg + reg_offset; reg_base 345 drivers/gpio/gpio-lynxpoint.c lg->reg_base = io_rc->start; reg_base 348 drivers/gpio/gpio-lynxpoint.c if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { reg_base 350 drivers/gpio/gpio-lynxpoint.c (unsigned int)lg->reg_base); reg_base 34 drivers/gpio/gpio-menz127.c void __iomem *reg_base; reg_base 69 drivers/gpio/gpio-menz127.c db_en = readl(priv->reg_base + MEN_Z127_DBER); reg_base 79 drivers/gpio/gpio-menz127.c writel(db_en, priv->reg_base + MEN_Z127_DBER); reg_base 80 drivers/gpio/gpio-menz127.c writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); reg_base 95 drivers/gpio/gpio-menz127.c od_en = readl(priv->reg_base + MEN_Z127_ODER); reg_base 103 drivers/gpio/gpio-menz127.c writel(od_en, priv->reg_base + MEN_Z127_ODER); reg_base 148 drivers/gpio/gpio-menz127.c men_z127_gpio->reg_base = ioremap(men_z127_gpio->mem->start, reg_base 150 drivers/gpio/gpio-menz127.c if (men_z127_gpio->reg_base == NULL) { reg_base 158 drivers/gpio/gpio-menz127.c men_z127_gpio->reg_base + MEN_Z127_PSR, reg_base 159 drivers/gpio/gpio-menz127.c men_z127_gpio->reg_base + MEN_Z127_CTRL, reg_base 161 drivers/gpio/gpio-menz127.c men_z127_gpio->reg_base + MEN_Z127_GPIODR, reg_base 179 drivers/gpio/gpio-menz127.c iounmap(men_z127_gpio->reg_base); reg_base 190 drivers/gpio/gpio-menz127.c iounmap(men_z127_gpio->reg_base); reg_base 52 drivers/gpio/gpio-merrifield.c void __iomem *reg_base; reg_base 92 drivers/gpio/gpio-merrifield.c return priv->reg_base + reg_type_offset + reg * 4; reg_base 429 drivers/gpio/gpio-merrifield.c priv->reg_base = pcim_iomap_table(pdev)[0]; reg_base 85 drivers/gpio/gpio-octeon.c void __iomem *reg_base; reg_base 93 drivers/gpio/gpio-octeon.c reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 94 drivers/gpio/gpio-octeon.c if (IS_ERR(reg_base)) reg_base 95 drivers/gpio/gpio-octeon.c return PTR_ERR(reg_base); reg_base 97 drivers/gpio/gpio-octeon.c gpio->register_base = (u64)reg_base; reg_base 41 drivers/gpio/gpio-sta2x11.c void __iomem *reg_base; reg_base 309 drivers/gpio/gpio-sta2x11.c chip->reg_base, handle_simple_irq); reg_base 362 drivers/gpio/gpio-sta2x11.c chip->reg_base = devm_platform_ioremap_resource(dev, 0); reg_base 363 drivers/gpio/gpio-sta2x11.c if (IS_ERR(chip->reg_base)) reg_base 364 drivers/gpio/gpio-sta2x11.c return PTR_ERR(chip->reg_base); reg_base 367 drivers/gpio/gpio-sta2x11.c chip->regs[i] = chip->reg_base + i * 4096; reg_base 201 drivers/gpio/gpio-tb10x.c gc->reg_base = tb10x_gpio->base; reg_base 115 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c *reg = adev->gfx.scratch.reg_base + i; reg_base 131 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); reg_base 100 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint32_t reg_base; reg_base 396 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); reg_base 1786 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c adev->gfx.scratch.reg_base = mmSCRATCH_REG0; reg_base 2072 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev->gfx.scratch.reg_base = mmSCRATCH_REG0; reg_base 832 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->gfx.scratch.reg_base = mmSCRATCH_REG0; reg_base 801 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); reg_base 353 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->gcu_addr = mdev->reg_base; reg_base 354 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->periph_addr = mdev->reg_base + (D71_BLOCK_OFFSET_PERIPH >> 2); reg_base 405 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c blk_base = mdev->reg_base + (offset >> 2); reg_base 578 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip) reg_base 580 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID); reg_base 581 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c chip->core_id = malidp_read32(reg_base, GLB_CORE_ID); reg_base 582 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO); reg_base 195 drivers/gpu/drm/arm/display/komeda/komeda_dev.c mdev->reg_base = devm_ioremap_resource(dev, io_res); reg_base 196 drivers/gpu/drm/arm/display/komeda/komeda_dev.c if (IS_ERR(mdev->reg_base)) { reg_base 198 drivers/gpu/drm/arm/display/komeda/komeda_dev.c err = PTR_ERR(mdev->reg_base); reg_base 199 drivers/gpu/drm/arm/display/komeda/komeda_dev.c mdev->reg_base = NULL; reg_base 213 drivers/gpu/drm/arm/display/komeda/komeda_dev.c mdev->funcs = product->identify(mdev->reg_base, &mdev->chip); reg_base 307 drivers/gpu/drm/arm/display/komeda/komeda_dev.c if (mdev->reg_base) { reg_base 308 drivers/gpu/drm/arm/display/komeda/komeda_dev.c devm_iounmap(dev, mdev->reg_base); reg_base 309 drivers/gpu/drm/arm/display/komeda/komeda_dev.c mdev->reg_base = NULL; reg_base 155 drivers/gpu/drm/arm/display/komeda/komeda_dev.h u32 __iomem *reg_base; reg_base 1698 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 1699 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (IS_ERR(dp->reg_base)) reg_base 1700 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c return ERR_CAST(dp->reg_base); reg_base 166 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h void __iomem *reg_base; reg_base 31 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 33 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 35 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 37 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 45 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 47 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 61 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); reg_base 69 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); reg_base 72 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); reg_base 79 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); reg_base 80 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); reg_base 81 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); reg_base 82 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); reg_base 83 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); reg_base 87 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); reg_base 91 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); reg_base 95 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); reg_base 101 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); reg_base 104 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); reg_base 105 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); reg_base 106 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); reg_base 107 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); reg_base 108 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 111 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); reg_base 112 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); reg_base 113 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); reg_base 114 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg_base 115 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg_base 133 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg_base 138 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 144 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg_base 145 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg_base 146 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 147 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 149 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 150 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); reg_base 152 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); reg_base 153 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); reg_base 155 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); reg_base 157 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); reg_base 159 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); reg_base 160 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); reg_base 162 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); reg_base 163 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); reg_base 165 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 170 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); reg_base 179 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); reg_base 182 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); reg_base 185 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); reg_base 188 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg_base 191 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg_base 199 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg_base 201 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg_base 203 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg_base 205 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg_base 214 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg_base 217 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg_base 224 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg_base 242 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + pd_addr); reg_base 247 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + pd_addr); reg_base 268 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 273 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 277 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 283 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 287 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 293 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 297 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 303 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 307 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 313 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 326 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg_base 332 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 339 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 342 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 345 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg_base 348 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + phy_pd_addr); reg_base 364 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); reg_base 366 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg_base 368 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg_base 385 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 388 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 400 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); reg_base 403 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 415 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 417 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 424 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 426 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 441 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); reg_base 461 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 463 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 472 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 490 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); reg_base 494 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); reg_base 497 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 499 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg_base 510 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 522 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg_base 524 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg_base 534 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg_base 536 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg_base 539 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 546 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 551 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 554 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 556 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 561 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); reg_base 582 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); reg_base 586 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); reg_base 588 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); reg_base 590 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); reg_base 594 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); reg_base 602 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); reg_base 621 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); reg_base 628 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); reg_base 637 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); reg_base 644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); reg_base 654 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 656 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 658 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 660 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 672 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 676 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 680 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 684 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 690 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 702 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg_base 705 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg_base 713 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg_base 716 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg_base 724 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg_base 727 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg_base 735 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg_base 738 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg_base 747 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg_base 756 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg_base 765 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg_base 774 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg_base 779 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg_base 784 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg_base 789 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg_base 794 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg_base 801 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); reg_base 803 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); reg_base 809 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); reg_base 817 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); reg_base 820 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg_base 823 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg_base 826 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 829 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); reg_base 840 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); reg_base 843 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg_base 849 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg_base 856 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg_base 857 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg_base 859 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg_base 866 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg_base 867 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg_base 869 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg_base 887 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 889 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 891 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); reg_base 893 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); reg_base 895 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); reg_base 898 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); reg_base 900 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); reg_base 902 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); reg_base 904 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 906 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg_base 908 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); reg_base 909 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); reg_base 910 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); reg_base 919 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 921 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 923 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 925 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 934 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 937 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 939 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 942 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 950 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 952 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg_base 959 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 960 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 962 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg_base 975 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg_base 982 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg_base 984 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 987 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 989 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 992 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 994 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 997 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg_base 1000 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg_base 1007 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 1009 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 1016 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 1018 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg_base 1023 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON); reg_base 1047 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1049 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1053 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); reg_base 1056 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); reg_base 1057 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); reg_base 1058 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); reg_base 1059 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); reg_base 1062 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0); reg_base 1063 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1); reg_base 1064 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2); reg_base 1065 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3); reg_base 1068 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); reg_base 1069 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); reg_base 1072 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg_base 1074 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg_base 1077 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1079 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1082 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1084 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); reg_base 1117 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); reg_base 1145 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); reg_base 1149 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); reg_base 1151 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); reg_base 1153 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); reg_base 1158 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg_base 1171 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg_base 1173 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2, reg_base 1182 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA, reg_base 1190 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 1193 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 1194 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c status_reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); reg_base 1196 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); reg_base 1205 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg_base 1213 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); reg_base 260 drivers/gpu/drm/exynos/exynos_drm_dsi.c void __iomem *reg_base; reg_base 322 drivers/gpu/drm/exynos/exynos_drm_dsi.c writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); reg_base 327 drivers/gpu/drm/exynos/exynos_drm_dsi.c return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); reg_base 614 drivers/gpu/drm/exynos/exynos_drm_dsi.c dsi->reg_base + driver_data->plltmr_reg); reg_base 1781 drivers/gpu/drm/exynos/exynos_drm_dsi.c dsi->reg_base = devm_ioremap_resource(dev, res); reg_base 1782 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (IS_ERR(dsi->reg_base)) { reg_base 1784 drivers/gpu/drm/exynos/exynos_drm_dsi.c return PTR_ERR(dsi->reg_base); reg_base 154 drivers/gpu/drm/i915/gvt/interrupt.c if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) reg_base 329 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) reg_base 331 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); reg_base 357 drivers/gpu/drm/i915/gvt/interrupt.c u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); reg_base 363 drivers/gpu/drm/i915/gvt/interrupt.c i915_mmio_reg_offset(up_irq_info->reg_base)); reg_base 365 drivers/gpu/drm/i915/gvt/interrupt.c i915_mmio_reg_offset(up_irq_info->reg_base)); reg_base 404 drivers/gpu/drm/i915/gvt/interrupt.c unsigned int reg_base; reg_base 411 drivers/gpu/drm/i915/gvt/interrupt.c reg_base = i915_mmio_reg_offset(info->reg_base); reg_base 415 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_imr(reg_base)))) { reg_base 418 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_iir(reg_base))); reg_base 440 drivers/gpu/drm/i915/gvt/interrupt.c .reg_base = (regbase), \ reg_base 459 drivers/gpu/drm/i915/gvt/interrupt.c .reg_base = SDEISR, reg_base 475 drivers/gpu/drm/i915/gvt/interrupt.c u32 reg_base; reg_base 480 drivers/gpu/drm/i915/gvt/interrupt.c reg_base = i915_mmio_reg_offset(info->reg_base); reg_base 481 drivers/gpu/drm/i915/gvt/interrupt.c if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) reg_base 482 drivers/gpu/drm/i915/gvt/interrupt.c & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) reg_base 175 drivers/gpu/drm/i915/gvt/interrupt.h i915_reg_t reg_base; reg_base 199 drivers/gpu/drm/i915/intel_wopcm.c u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); reg_base 203 drivers/gpu/drm/i915/intel_wopcm.c !(reg_base & GUC_WOPCM_OFFSET_VALID)) reg_base 206 drivers/gpu/drm/i915/intel_wopcm.c *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK; reg_base 541 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", reg_base 543 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c if (IS_ERR(phy->reg_base)) { reg_base 78 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h void __iomem *reg_base; reg_base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c void __iomem *base = phy->reg_base; reg_base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c void __iomem *base = phy->reg_base; reg_base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; reg_base 56 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; reg_base 67 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; reg_base 3441 drivers/gpu/drm/radeon/cik.c rdev->scratch.reg_base = SCRATCH_REG0; reg_base 3444 drivers/gpu/drm/radeon/cik.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg_base 2815 drivers/gpu/drm/radeon/r600.c rdev->scratch.reg_base = SCRATCH_REG0; reg_base 2818 drivers/gpu/drm/radeon/r600.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg_base 706 drivers/gpu/drm/radeon/radeon.h uint32_t reg_base; reg_base 276 drivers/gpu/drm/radeon/radeon_device.c rdev->scratch.reg_base = RADEON_SCRATCH_REG0; reg_base 279 drivers/gpu/drm/radeon/radeon_device.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg_base 862 drivers/gpu/drm/radeon/radeon_fence.c rdev->scratch.reg_base; reg_base 3367 drivers/gpu/drm/radeon/si.c rdev->scratch.reg_base = SCRATCH_REG0; reg_base 3370 drivers/gpu/drm/radeon/si.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg_base 1300 drivers/gpu/ipu-v3/ipu-common.c gc->reg_base = ipu->cm_reg; reg_base 130 drivers/hwtracing/intel_th/msu.c void __iomem *reg_base; reg_base 773 drivers/hwtracing/intel_th/msu.c msc->orig_addr = ioread32(msc->reg_base + REG_MSU_MSC0BAR); reg_base 774 drivers/hwtracing/intel_th/msu.c msc->orig_sz = ioread32(msc->reg_base + REG_MSU_MSC0SIZE); reg_base 777 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0BAR); reg_base 781 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0SIZE); reg_base 784 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); reg_base 794 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); reg_base 831 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0STS); reg_base 834 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0MWP); reg_base 840 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); reg_base 842 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); reg_base 850 drivers/hwtracing/intel_th/msu.c iowrite32(msc->orig_addr, msc->reg_base + REG_MSU_MSC0BAR); reg_base 851 drivers/hwtracing/intel_th/msu.c iowrite32(msc->orig_sz, msc->reg_base + REG_MSU_MSC0SIZE); reg_base 854 drivers/hwtracing/intel_th/msu.c ioread32(msc->reg_base + REG_MSU_MSC0NWSA)); reg_base 856 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0STS); reg_base 859 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSUSTS); reg_base 861 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSUSTS); reg_base 1656 drivers/hwtracing/intel_th/msu.c reg = __raw_readl(msc->reg_base + REG_MSU_MSC0STS); reg_base 1674 drivers/hwtracing/intel_th/msu.c (ioread32(msc->reg_base + REG_MSU_MSC0CTL) & MSC_LEN) >> reg_base 2089 drivers/hwtracing/intel_th/msu.c msc->reg_base = base + msc->index * 0x100; reg_base 126 drivers/i2c/busses/i2c-mv64xxx.c void __iomem *reg_base; reg_base 206 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); reg_base 207 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); reg_base 208 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + reg_base 210 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + reg_base 214 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); reg_base 216 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.clock); reg_base 217 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); reg_base 218 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); reg_base 220 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 342 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 370 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 375 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_base 377 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 382 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_base 384 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 389 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.data); reg_base 391 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 396 drivers/i2c/busses/i2c-mv64xxx.c readl(drv_data->reg_base + drv_data->reg_offsets.data); reg_base 398 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 403 drivers/i2c/busses/i2c-mv64xxx.c readl(drv_data->reg_base + drv_data->reg_offsets.data); reg_base 406 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 425 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 438 drivers/i2c/busses/i2c-mv64xxx.c buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO); reg_base 439 drivers/i2c/busses/i2c-mv64xxx.c buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI); reg_base 449 drivers/i2c/busses/i2c-mv64xxx.c cause = readl(drv_data->reg_base + reg_base 454 drivers/i2c/busses/i2c-mv64xxx.c status = readl(drv_data->reg_base + reg_base 486 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); reg_base 487 drivers/i2c/busses/i2c-mv64xxx.c writel(0, drv_data->reg_base + reg_base 509 drivers/i2c/busses/i2c-mv64xxx.c while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & reg_base 511 drivers/i2c/busses/i2c-mv64xxx.c status = readl(drv_data->reg_base + drv_data->reg_offsets.status); reg_base 517 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base + drv_data->reg_offsets.control); reg_base 598 drivers/i2c/busses/i2c-mv64xxx.c writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); reg_base 599 drivers/i2c/busses/i2c-mv64xxx.c writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); reg_base 653 drivers/i2c/busses/i2c-mv64xxx.c writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); reg_base 892 drivers/i2c/busses/i2c-mv64xxx.c drv_data->reg_base = devm_ioremap_resource(&pd->dev, r); reg_base 893 drivers/i2c/busses/i2c-mv64xxx.c if (IS_ERR(drv_data->reg_base)) reg_base 894 drivers/i2c/busses/i2c-mv64xxx.c return PTR_ERR(drv_data->reg_base); reg_base 30 drivers/i2c/busses/i2c-pca-platform.c void __iomem *reg_base; reg_base 45 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg); reg_base 51 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg * 2); reg_base 57 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg * 4); reg_base 63 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg); reg_base 69 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 2); reg_base 75 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 4); reg_base 153 drivers/i2c/busses/i2c-pca-platform.c i2c->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 154 drivers/i2c/busses/i2c-pca-platform.c if (IS_ERR(i2c->reg_base)) reg_base 155 drivers/i2c/busses/i2c-pca-platform.c return PTR_ERR(i2c->reg_base); reg_base 190 drivers/i2c/busses/i2c-pxa.c void __iomem *reg_base; reg_base 1216 drivers/i2c/busses/i2c-pxa.c i2c->reg_base = devm_ioremap_resource(&dev->dev, res); reg_base 1217 drivers/i2c/busses/i2c-pxa.c if (IS_ERR(i2c->reg_base)) reg_base 1218 drivers/i2c/busses/i2c-pxa.c return PTR_ERR(i2c->reg_base); reg_base 1249 drivers/i2c/busses/i2c-pxa.c i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; reg_base 1250 drivers/i2c/busses/i2c-pxa.c i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; reg_base 1251 drivers/i2c/busses/i2c-pxa.c i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; reg_base 1252 drivers/i2c/busses/i2c-pxa.c i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; reg_base 1257 drivers/i2c/busses/i2c-pxa.c i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; reg_base 1260 drivers/i2c/busses/i2c-pxa.c i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr; reg_base 1261 drivers/i2c/busses/i2c-pxa.c i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr; reg_base 20 drivers/i2c/busses/i2c-sibyte.c void *reg_base; /* CSR base */ reg_base 24 drivers/i2c/busses/i2c-sibyte.c #define SMB_CSR(a,r) ((long)(a->reg_base + r)) reg_base 60 drivers/i2c/busses/i2c-zx2967.c void __iomem *reg_base; reg_base 72 drivers/i2c/busses/i2c-zx2967.c writel_relaxed(val, i2c->reg_base + reg); reg_base 77 drivers/i2c/busses/i2c-zx2967.c return readl_relaxed(i2c->reg_base + reg); reg_base 83 drivers/i2c/busses/i2c-zx2967.c writesb(i2c->reg_base + reg, data, len); reg_base 89 drivers/i2c/busses/i2c-zx2967.c readsb(i2c->reg_base + reg, data, len); reg_base 504 drivers/i2c/busses/i2c-zx2967.c void __iomem *reg_base; reg_base 514 drivers/i2c/busses/i2c-zx2967.c reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 515 drivers/i2c/busses/i2c-zx2967.c if (IS_ERR(reg_base)) reg_base 516 drivers/i2c/busses/i2c-zx2967.c return PTR_ERR(reg_base); reg_base 542 drivers/i2c/busses/i2c-zx2967.c i2c->reg_base = reg_base; reg_base 30 drivers/ide/opti621.c static int reg_base; reg_base 41 drivers/ide/opti621.c inw(reg_base + 1); reg_base 42 drivers/ide/opti621.c inw(reg_base + 1); reg_base 43 drivers/ide/opti621.c outb(3, reg_base + 2); reg_base 44 drivers/ide/opti621.c outb(value, reg_base + reg); reg_base 45 drivers/ide/opti621.c outb(0x83, reg_base + 2); reg_base 57 drivers/ide/opti621.c inw(reg_base + 1); reg_base 58 drivers/ide/opti621.c inw(reg_base + 1); reg_base 59 drivers/ide/opti621.c outb(3, reg_base + 2); reg_base 60 drivers/ide/opti621.c ret = inb(reg_base + reg); reg_base 61 drivers/ide/opti621.c outb(0x83, reg_base + 2); reg_base 94 drivers/ide/opti621.c reg_base = hwif->io_ports.data_addr; reg_base 97 drivers/ide/opti621.c outb(0xc0, reg_base + CNTRL_REG); reg_base 99 drivers/ide/opti621.c outb(0xff, reg_base + 5); reg_base 101 drivers/ide/opti621.c (void)inb(reg_base + CNTRL_REG); reg_base 141 drivers/iio/adc/at91_adc.c (readl_relaxed(st->reg_base + reg)) reg_base 143 drivers/iio/adc/at91_adc.c (writel_relaxed(val, st->reg_base + reg)) reg_base 204 drivers/iio/adc/at91_adc.c void __iomem *reg_base; reg_base 1187 drivers/iio/adc/at91_adc.c st->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 1188 drivers/iio/adc/at91_adc.c if (IS_ERR(st->reg_base)) reg_base 1189 drivers/iio/adc/at91_adc.c return PTR_ERR(st->reg_base); reg_base 56 drivers/iio/adc/cc10001_adc.c void __iomem *reg_base; reg_base 70 drivers/iio/adc/cc10001_adc.c writel(val, adc_dev->reg_base + reg); reg_base 76 drivers/iio/adc/cc10001_adc.c return readl(adc_dev->reg_base + reg); reg_base 344 drivers/iio/adc/cc10001_adc.c adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 345 drivers/iio/adc/cc10001_adc.c if (IS_ERR(adc_dev->reg_base)) { reg_base 346 drivers/iio/adc/cc10001_adc.c ret = PTR_ERR(adc_dev->reg_base); reg_base 43 drivers/iio/adc/mt6577_auxadc.c void __iomem *reg_base; reg_base 109 drivers/iio/adc/mt6577_auxadc.c reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 + reg_base 114 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, reg_base 130 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, reg_base 138 drivers/iio/adc/mt6577_auxadc.c ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2, reg_base 217 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, reg_base 229 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, reg_base 257 drivers/iio/adc/mt6577_auxadc.c adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 258 drivers/iio/adc/mt6577_auxadc.c if (IS_ERR(adc_dev->reg_base)) { reg_base 260 drivers/iio/adc/mt6577_auxadc.c return PTR_ERR(adc_dev->reg_base); reg_base 284 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, reg_base 299 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, reg_base 313 drivers/iio/adc/mt6577_auxadc.c mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, reg_base 380 drivers/iio/adc/twl4030-madc.c u8 reg_base, unsigned reg_base 389 drivers/iio/adc/twl4030-madc.c reg = reg_base + (2 * i); reg_base 40 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) reg_base 41 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_read(dev, reg) readl((dev)->reg_base + (reg)) reg_base 371 drivers/infiniband/hw/hns/hns_roce_cq.c hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset + reg_base 1014 drivers/infiniband/hw/hns/hns_roce_device.h u8 __iomem *reg_base; reg_base 405 drivers/infiniband/hw/hns/hns_roce_hem.c bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG; reg_base 430 drivers/infiniband/hw/hns/hns_roce_hem.c hr_dev->reg_base + ROCEE_BT_CMD_L_REG); reg_base 1667 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG); reg_base 1676 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG); reg_base 1716 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG; reg_base 1752 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG + reg_base 1756 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG + reg_base 1760 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG + reg_base 1764 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG + reg_base 1797 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG + reg_base 2459 drivers/infiniband/hw/hns/hns_roce_hw_v1.c bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG; reg_base 2479 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG); reg_base 2664 drivers/infiniband/hw/hns/hns_roce_hw_v1.c addr = (u32 __iomem *)(hr_dev->reg_base + reg_base 3287 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hr_qp->rq.db_reg_l = hr_dev->reg_base + reg_base 4338 drivers/infiniband/hw/hns/hns_roce_hw_v1.c eq_table->eqc_base[i] = hr_dev->reg_base + reg_base 4342 drivers/infiniband/hw/hns/hns_roce_hw_v1.c eq->doorbell = hr_dev->reg_base + reg_base 4350 drivers/infiniband/hw/hns/hns_roce_hw_v1.c eq_table->eqc_base[i] = hr_dev->reg_base + reg_base 4353 drivers/infiniband/hw/hns/hns_roce_hw_v1.c eq->doorbell = hr_dev->reg_base + reg_base 4547 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0); reg_base 4548 drivers/infiniband/hw/hns/hns_roce_hw_v1.c if (IS_ERR(hr_dev->reg_base)) reg_base 4549 drivers/infiniband/hw/hns/hns_roce_hw_v1.c return PTR_ERR(hr_dev->reg_base); reg_base 5405 drivers/infiniband/hw/hns/hns_roce_hw_v2.c eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; reg_base 6393 drivers/infiniband/hw/hns/hns_roce_hw_v2.c hr_dev->reg_base = handle->rinfo.roce_io_base; reg_base 831 drivers/infiniband/hw/hns/hns_roce_qp.c hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + reg_base 833 drivers/infiniband/hw/hns/hns_roce_qp.c hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + reg_base 411 drivers/infiniband/hw/hns/hns_roce_srq.c srq->db_reg_l = hr_dev->reg_base + SRQ_DB_REG; reg_base 64 drivers/input/keyboard/nomadik-ske-keypad.c void __iomem *reg_base; reg_base 80 drivers/input/keyboard/nomadik-ske-keypad.c ret = readl(keypad->reg_base + addr); reg_base 83 drivers/input/keyboard/nomadik-ske-keypad.c writel(ret, keypad->reg_base + addr); reg_base 99 drivers/input/keyboard/nomadik-ske-keypad.c while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--) reg_base 111 drivers/input/keyboard/nomadik-ske-keypad.c value = readl(keypad->reg_base + SKE_DBCR); reg_base 114 drivers/input/keyboard/nomadik-ske-keypad.c writel(value, keypad->reg_base + SKE_DBCR); reg_base 155 drivers/input/keyboard/nomadik-ske-keypad.c ske_ris = readl(keypad->reg_base + SKE_RIS); reg_base 179 drivers/input/keyboard/nomadik-ske-keypad.c ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i)); reg_base 206 drivers/input/keyboard/nomadik-ske-keypad.c while ((readl(keypad->reg_base + SKE_CR) & SKE_KPASON) && --timeout) reg_base 213 drivers/input/keyboard/nomadik-ske-keypad.c while ((readl(keypad->reg_base + SKE_RIS)) && --timeout) reg_base 266 drivers/input/keyboard/nomadik-ske-keypad.c keypad->reg_base = ioremap(res->start, resource_size(res)); reg_base 267 drivers/input/keyboard/nomadik-ske-keypad.c if (!keypad->reg_base) { reg_base 358 drivers/input/keyboard/nomadik-ske-keypad.c iounmap(keypad->reg_base); reg_base 382 drivers/input/keyboard/nomadik-ske-keypad.c iounmap(keypad->reg_base); reg_base 32 drivers/input/keyboard/nspire-keypad.c void __iomem *reg_base; reg_base 61 drivers/input/keyboard/nspire-keypad.c int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask; reg_base 65 drivers/input/keyboard/nspire-keypad.c memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state)); reg_base 91 drivers/input/keyboard/nspire-keypad.c writel(0x3, keypad->reg_base + KEYPAD_INT); reg_base 115 drivers/input/keyboard/nspire-keypad.c writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); reg_base 118 drivers/input/keyboard/nspire-keypad.c writel(val, keypad->reg_base + KEYPAD_CNTL); reg_base 122 drivers/input/keyboard/nspire-keypad.c writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK); reg_base 126 drivers/input/keyboard/nspire-keypad.c writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT); reg_base 128 drivers/input/keyboard/nspire-keypad.c writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS); reg_base 203 drivers/input/keyboard/nspire-keypad.c keypad->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 204 drivers/input/keyboard/nspire-keypad.c if (IS_ERR(keypad->reg_base)) reg_base 205 drivers/input/keyboard/nspire-keypad.c return PTR_ERR(keypad->reg_base); reg_base 915 drivers/input/misc/ad714x.c unsigned short reg_base; reg_base 921 drivers/input/misc/ad714x.c reg_base = AD714X_STAGECFG_REG + i * STAGE_CFGREG_NUM; reg_base 923 drivers/input/misc/ad714x.c ad714x->write(ad714x, reg_base + j, reg_base 2093 drivers/input/mouse/alps.c int reg_base, bool enable) reg_base 2100 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x0008); reg_base 2133 drivers/input/mouse/alps.c static int alps_probe_trackstick_v3_v7(struct psmouse *psmouse, int reg_base) reg_base 2140 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08); reg_base 2152 drivers/input/mouse/alps.c static int alps_setup_trackstick_v3(struct psmouse *psmouse, int reg_base) reg_base 2166 drivers/input/mouse/alps.c if (alps_passthrough_mode_v3(psmouse, reg_base, true)) reg_base 2189 drivers/input/mouse/alps.c if (alps_passthrough_mode_v3(psmouse, reg_base, false)) reg_base 2198 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08); reg_base 85 drivers/input/serio/sun4i-ps2.c void __iomem *reg_base; reg_base 107 drivers/input/serio/sun4i-ps2.c intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); reg_base 108 drivers/input/serio/sun4i-ps2.c fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); reg_base 118 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_LSTS); reg_base 125 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_FSTS); reg_base 130 drivers/input/serio/sun4i-ps2.c byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; reg_base 134 drivers/input/serio/sun4i-ps2.c writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); reg_base 135 drivers/input/serio/sun4i-ps2.c writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); reg_base 154 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_LCTL); reg_base 161 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_FCTL); reg_base 168 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_CLKDR); reg_base 175 drivers/input/serio/sun4i-ps2.c writel(rval, drvdata->reg_base + PS2_REG_GCTL); reg_base 187 drivers/input/serio/sun4i-ps2.c rval = readl(drvdata->reg_base + PS2_REG_GCTL); reg_base 188 drivers/input/serio/sun4i-ps2.c writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL); reg_base 199 drivers/input/serio/sun4i-ps2.c if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) { reg_base 200 drivers/input/serio/sun4i-ps2.c writel(val, drvdata->reg_base + PS2_REG_DATA); reg_base 234 drivers/input/serio/sun4i-ps2.c drvdata->reg_base = ioremap(res->start, resource_size(res)); reg_base 235 drivers/input/serio/sun4i-ps2.c if (!drvdata->reg_base) { reg_base 264 drivers/input/serio/sun4i-ps2.c writel(0, drvdata->reg_base + PS2_REG_GCTL); reg_base 296 drivers/input/serio/sun4i-ps2.c iounmap(drvdata->reg_base); reg_base 314 drivers/input/serio/sun4i-ps2.c iounmap(drvdata->reg_base); reg_base 166 drivers/irqchip/irq-al-fic.c gc->reg_base = fic->base; reg_base 216 drivers/irqchip/irq-atmel-aic-common.c void __iomem *reg_base; reg_base 223 drivers/irqchip/irq-atmel-aic-common.c reg_base = of_iomap(node, 0); reg_base 224 drivers/irqchip/irq-atmel-aic-common.c if (!reg_base) reg_base 249 drivers/irqchip/irq-atmel-aic-common.c gc->reg_base = reg_base; reg_base 272 drivers/irqchip/irq-atmel-aic-common.c iounmap(reg_base); reg_base 288 drivers/irqchip/irq-bcm7120-l2.c gc->reg_base = data->pair_base[idx]; reg_base 224 drivers/irqchip/irq-brcmstb-l2.c data->gc->reg_base = base; reg_base 34 drivers/irqchip/irq-csky-apb-intc.c static void __iomem *reg_base; reg_base 60 drivers/irqchip/irq-csky-apb-intc.c static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, reg_base 66 drivers/irqchip/irq-csky-apb-intc.c gc->reg_base = reg_base; reg_base 111 drivers/irqchip/irq-csky-apb-intc.c reg_base = of_iomap(node, 0); reg_base 112 drivers/irqchip/irq-csky-apb-intc.c if (!reg_base) { reg_base 153 drivers/irqchip/irq-csky-apb-intc.c readl(reg_base + GX_INTC_PEN63_32), 32); reg_base 158 drivers/irqchip/irq-csky-apb-intc.c readl(reg_base + GX_INTC_PEN31_00), 0); reg_base 175 drivers/irqchip/irq-csky-apb-intc.c writel(0x0, reg_base + GX_INTC_NEN31_00); reg_base 176 drivers/irqchip/irq-csky-apb-intc.c writel(0x0, reg_base + GX_INTC_NEN63_32); reg_base 181 drivers/irqchip/irq-csky-apb-intc.c writel(0x0, reg_base + GX_INTC_NMASK31_00); reg_base 182 drivers/irqchip/irq-csky-apb-intc.c writel(0x0, reg_base + GX_INTC_NMASK63_32); reg_base 184 drivers/irqchip/irq-csky-apb-intc.c setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE); reg_base 186 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0); reg_base 187 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32); reg_base 202 drivers/irqchip/irq-csky-apb-intc.c void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00; reg_base 203 drivers/irqchip/irq-csky-apb-intc.c void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32; reg_base 240 drivers/irqchip/irq-csky-apb-intc.c writel(0, reg_base + CK_INTC_NEN31_00); reg_base 241 drivers/irqchip/irq-csky-apb-intc.c writel(0, reg_base + CK_INTC_NEN63_32); reg_base 244 drivers/irqchip/irq-csky-apb-intc.c writel(BIT(31), reg_base + CK_INTC_ICR); reg_base 246 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0); reg_base 247 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32); reg_base 249 drivers/irqchip/irq-csky-apb-intc.c setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE); reg_base 270 drivers/irqchip/irq-csky-apb-intc.c writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE); reg_base 271 drivers/irqchip/irq-csky-apb-intc.c writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE); reg_base 273 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64); reg_base 274 drivers/irqchip/irq-csky-apb-intc.c ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96); reg_base 277 drivers/irqchip/irq-csky-apb-intc.c reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE); reg_base 75 drivers/irqchip/irq-csky-mpintc.c void __iomem *reg_base = this_cpu_read(intcl_reg); reg_base 78 drivers/irqchip/irq-csky-mpintc.c readl_relaxed(reg_base + INTCL_RDYIR), regs); reg_base 83 drivers/irqchip/irq-csky-mpintc.c void __iomem *reg_base = this_cpu_read(intcl_reg); reg_base 87 drivers/irqchip/irq-csky-mpintc.c writel_relaxed(d->hwirq, reg_base + INTCL_SENR); reg_base 92 drivers/irqchip/irq-csky-mpintc.c void __iomem *reg_base = this_cpu_read(intcl_reg); reg_base 94 drivers/irqchip/irq-csky-mpintc.c writel_relaxed(d->hwirq, reg_base + INTCL_CENR); reg_base 99 drivers/irqchip/irq-csky-mpintc.c void __iomem *reg_base = this_cpu_read(intcl_reg); reg_base 101 drivers/irqchip/irq-csky-mpintc.c writel_relaxed(d->hwirq, reg_base + INTCL_CACR); reg_base 215 drivers/irqchip/irq-csky-mpintc.c void __iomem *reg_base = this_cpu_read(intcl_reg); reg_base 222 drivers/irqchip/irq-csky-mpintc.c reg_base + INTCL_SIGR); reg_base 50 drivers/irqchip/irq-davinci-aintc.c gc->reg_base = base; reg_base 57 drivers/irqchip/irq-digicolor.c static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, reg_base 63 drivers/irqchip/irq-digicolor.c gc->reg_base = reg_base; reg_base 74 drivers/irqchip/irq-digicolor.c void __iomem *reg_base; reg_base 79 drivers/irqchip/irq-digicolor.c reg_base = of_iomap(node, 0); reg_base 80 drivers/irqchip/irq-digicolor.c if (!reg_base) { reg_base 86 drivers/irqchip/irq-digicolor.c writel(0, reg_base + IC_INT0ENABLE_LO); reg_base 87 drivers/irqchip/irq-digicolor.c writel(0, reg_base + IC_INT0ENABLE_XLO); reg_base 112 drivers/irqchip/irq-digicolor.c digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); reg_base 113 drivers/irqchip/irq-digicolor.c digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); reg_base 39 drivers/irqchip/irq-dw-apb-ictl.c u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); reg_base 60 drivers/irqchip/irq-dw-apb-ictl.c writel_relaxed(~0, gc->reg_base + ct->regs.enable); reg_base 61 drivers/irqchip/irq-dw-apb-ictl.c writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); reg_base 141 drivers/irqchip/irq-dw-apb-ictl.c gc->reg_base = iobase + i * APB_INT_BASE_OFFSET; reg_base 404 drivers/irqchip/irq-imgpdc.c gc->reg_base = priv->pdc_base; reg_base 418 drivers/irqchip/irq-imgpdc.c gc->reg_base = priv->pdc_base; reg_base 57 drivers/irqchip/irq-ingenic.c writel(mask, gc->reg_base + regs->enable); reg_base 58 drivers/irqchip/irq-ingenic.c writel(~mask, gc->reg_base + regs->disable); reg_base 65 drivers/irqchip/irq-ls1x.c writel(readl(gc->reg_base + offset) | mask, reg_base 66 drivers/irqchip/irq-ls1x.c gc->reg_base + offset); reg_base 68 drivers/irqchip/irq-ls1x.c writel(readl(gc->reg_base + offset) & ~mask, reg_base 69 drivers/irqchip/irq-ls1x.c gc->reg_base + offset); reg_base 157 drivers/irqchip/irq-ls1x.c gc->reg_base = priv->intc_base; reg_base 88 drivers/irqchip/irq-mscc-ocelot.c gc->reg_base = of_iomap(node, 0); reg_base 89 drivers/irqchip/irq-mscc-ocelot.c if (!gc->reg_base) { reg_base 124 drivers/irqchip/irq-nvic.c gc->reg_base = nvic_base + 4 * i; reg_base 135 drivers/irqchip/irq-nvic.c writel_relaxed(~0, gc->reg_base + NVIC_ICER); reg_base 205 drivers/irqchip/irq-omap-intc.c gc->reg_base = base; reg_base 41 drivers/irqchip/irq-orion.c u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & reg_base 86 drivers/irqchip/irq-orion.c gc->reg_base = ioremap(r.start, resource_size(&r)); reg_base 87 drivers/irqchip/irq-orion.c if (!gc->reg_base) reg_base 95 drivers/irqchip/irq-orion.c writel(0, gc->reg_base + ORION_IRQ_MASK); reg_base 114 drivers/irqchip/irq-orion.c u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & reg_base 183 drivers/irqchip/irq-orion.c gc->reg_base = ioremap(r.start, resource_size(&r)); reg_base 184 drivers/irqchip/irq-orion.c if (!gc->reg_base) { reg_base 197 drivers/irqchip/irq-orion.c writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); reg_base 198 drivers/irqchip/irq-orion.c writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE); reg_base 263 drivers/irqchip/irq-pic32-evic.c gc->reg_base = evic_base; reg_base 187 drivers/irqchip/irq-renesas-irqc.c p->gc->reg_base = p->cpu_int_base; reg_base 1229 drivers/irqchip/irq-s3c24xx.c void __iomem *reg_base; reg_base 1232 drivers/irqchip/irq-s3c24xx.c reg_base = of_iomap(np, 0); reg_base 1233 drivers/irqchip/irq-s3c24xx.c if (!reg_base) { reg_base 1263 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = reg_base + ctrl->offset; reg_base 1264 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = reg_base + ctrl->offset + 0x4; reg_base 1276 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = reg_base + ctrl->offset; reg_base 1277 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = reg_base + ctrl->offset + 0x08; reg_base 1278 drivers/irqchip/irq-s3c24xx.c intc->reg_intpnd = reg_base + ctrl->offset + 0x10; reg_base 50 drivers/irqchip/irq-sirfsoc.c gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET; reg_base 753 drivers/irqchip/irq-stm32-exti.c gc->reg_base = host_data->base; reg_base 191 drivers/irqchip/irq-sunxi-nmi.c gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node)); reg_base 192 drivers/irqchip/irq-sunxi-nmi.c if (IS_ERR(gc->reg_base)) { reg_base 194 drivers/irqchip/irq-sunxi-nmi.c ret = PTR_ERR(gc->reg_base); reg_base 134 drivers/irqchip/irq-tango.c gc->reg_base = chip->base; reg_base 103 drivers/irqchip/irq-tb10x.c void __iomem *reg_base; reg_base 117 drivers/irqchip/irq-tb10x.c reg_base = ioremap(mem.start, resource_size(&mem)); reg_base 118 drivers/irqchip/irq-tb10x.c if (!reg_base) { reg_base 144 drivers/irqchip/irq-tb10x.c gc->reg_base = reg_base; reg_base 179 drivers/irqchip/irq-tb10x.c iounmap(reg_base); reg_base 26 drivers/irqchip/irq-uniphier-aidet.c void __iomem *reg_base; reg_base 38 drivers/irqchip/irq-uniphier-aidet.c tmp = readl_relaxed(priv->reg_base + reg); reg_base 41 drivers/irqchip/irq-uniphier-aidet.c writel_relaxed(tmp, priv->reg_base + reg); reg_base 183 drivers/irqchip/irq-uniphier-aidet.c priv->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 184 drivers/irqchip/irq-uniphier-aidet.c if (IS_ERR(priv->reg_base)) reg_base 185 drivers/irqchip/irq-uniphier-aidet.c return PTR_ERR(priv->reg_base); reg_base 209 drivers/irqchip/irq-uniphier-aidet.c priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4); reg_base 221 drivers/irqchip/irq-uniphier-aidet.c priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4); reg_base 44 drivers/irqchip/irq-zevio.c readl(gc->reg_base + regs->ack); reg_base 105 drivers/irqchip/irq-zevio.c gc->reg_base = zevio_irq_io; reg_base 170 drivers/macintosh/windfarm_fcu_controls.c int rc, reg_base, shift = pv->rpm_shift; reg_base 188 drivers/macintosh/windfarm_fcu_controls.c reg_base = 0x11; reg_base 190 drivers/macintosh/windfarm_fcu_controls.c reg_base = 0x10; reg_base 192 drivers/macintosh/windfarm_fcu_controls.c rc = wf_fcu_read_reg(pv, reg_base + (fan->id * 2), buf, 2); reg_base 50 drivers/mailbox/stm32-ipcc.c void __iomem *reg_base; reg_base 240 drivers/mailbox/stm32-ipcc.c ipcc->reg_base = devm_ioremap_resource(dev, res); reg_base 241 drivers/mailbox/stm32-ipcc.c if (IS_ERR(ipcc->reg_base)) reg_base 242 drivers/mailbox/stm32-ipcc.c return PTR_ERR(ipcc->reg_base); reg_base 244 drivers/mailbox/stm32-ipcc.c ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; reg_base 302 drivers/mailbox/stm32-ipcc.c ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR); reg_base 326 drivers/mailbox/stm32-ipcc.c ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER); reg_base 134 drivers/media/pci/solo6x10/solo6x10-core.c if (solo_dev->reg_base) { reg_base 148 drivers/media/pci/solo6x10/solo6x10-core.c pci_iounmap(pdev, solo_dev->reg_base); reg_base 486 drivers/media/pci/solo6x10/solo6x10-core.c solo_dev->reg_base = pci_ioremap_bar(pdev, 0); reg_base 487 drivers/media/pci/solo6x10/solo6x10-core.c if (solo_dev->reg_base == NULL) { reg_base 188 drivers/media/pci/solo6x10/solo6x10.h u8 __iomem *reg_base; reg_base 277 drivers/media/pci/solo6x10/solo6x10.h return readl(solo_dev->reg_base + reg); reg_base 285 drivers/media/pci/solo6x10/solo6x10.h writel(data, solo_dev->reg_base + reg); reg_base 46 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] + reg_base 52 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c cg_status = readl(dev->reg_base[0]); reg_base 67 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG); reg_base 69 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG); reg_base 262 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c dev->reg_base[i] = devm_ioremap_resource(&pdev->dev, res); reg_base 263 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c if (IS_ERR((__force void *)dev->reg_base[i])) { reg_base 264 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c ret = PTR_ERR((__force void *)dev->reg_base[i]); reg_base 267 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c mtk_v4l2_debug(2, "reg[%d] base=%p", i, dev->reg_base[i]); reg_base 351 drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE]; reg_base 70 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c addr = dev->reg_base[VENC_SYS] + MTK_VENC_IRQ_ACK_OFFSET; reg_base 72 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c ctx->irq_status = readl(dev->reg_base[VENC_SYS] + reg_base 93 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c ctx->irq_status = readl(dev->reg_base[VENC_LT_SYS] + reg_base 96 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c addr = dev->reg_base[VENC_LT_SYS] + MTK_VENC_IRQ_ACK_OFFSET; reg_base 264 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c dev->reg_base[i] = devm_ioremap_resource(&pdev->dev, res); reg_base 265 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c if (IS_ERR((__force void *)dev->reg_base[i])) { reg_base 266 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c ret = PTR_ERR((__force void *)dev->reg_base[i]); reg_base 269 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c mtk_v4l2_debug(2, "reg[%d] base=0x%p", i, dev->reg_base[i]); reg_base 33 drivers/media/platform/mtk-vcodec/mtk_vcodec_util.c return ctx->dev->reg_base[reg_idx]; reg_base 161 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c struct vdec_vp8_hw_reg_base reg_base; reg_base 170 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.top = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP); reg_base 171 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.cm = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM); reg_base 172 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.hwd = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD); reg_base 173 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.sys = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS); reg_base 174 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.misc = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC); reg_base 175 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.ld = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD); reg_base 176 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c inst->reg_base.hwb = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB); reg_base 184 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *cm = inst->reg_base.cm; reg_base 187 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4; reg_base 205 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *cm = inst->reg_base.cm; reg_base 208 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4; reg_base 225 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *sys = inst->reg_base.sys; reg_base 226 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *misc = inst->reg_base.misc; reg_base 227 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *ld = inst->reg_base.ld; reg_base 228 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *hwb = inst->reg_base.hwb; reg_base 229 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *hwd = inst->reg_base.hwd; reg_base 253 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *hwd = inst->reg_base.hwd; reg_base 271 drivers/media/platform/mtk-vcodec/vdec/vdec_vp8_if.c void __iomem *hwd = inst->reg_base.hwd; reg_base 98 drivers/media/rc/img-ir/img-ir-core.c priv->reg_base = devm_ioremap_resource(&pdev->dev, res_regs); reg_base 99 drivers/media/rc/img-ir/img-ir-core.c if (IS_ERR(priv->reg_base)) reg_base 100 drivers/media/rc/img-ir/img-ir-core.c return PTR_ERR(priv->reg_base); reg_base 148 drivers/media/rc/img-ir/img-ir.h void __iomem *reg_base; reg_base 160 drivers/media/rc/img-ir/img-ir.h iowrite32(data, priv->reg_base + reg_offs); reg_base 166 drivers/media/rc/img-ir/img-ir.h return ioread32(priv->reg_base + reg_offs); reg_base 46 drivers/memory/samsung/exynos-srom.c void __iomem *reg_base; reg_base 90 drivers/memory/samsung/exynos-srom.c bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW); reg_base 92 drivers/memory/samsung/exynos-srom.c writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW); reg_base 100 drivers/memory/samsung/exynos-srom.c srom->reg_base + EXYNOS_SROM_BC0 + bank); reg_base 124 drivers/memory/samsung/exynos-srom.c srom->reg_base = of_iomap(np, 0); reg_base 125 drivers/memory/samsung/exynos-srom.c if (!srom->reg_base) { reg_base 135 drivers/memory/samsung/exynos-srom.c iounmap(srom->reg_base); reg_base 179 drivers/memory/samsung/exynos-srom.c exynos_srom_save(srom->reg_base, srom->reg_offset, reg_base 188 drivers/memory/samsung/exynos-srom.c exynos_srom_restore(srom->reg_base, srom->reg_offset, reg_base 53 drivers/mmc/host/android-goldfish.c #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr)) reg_base 54 drivers/mmc/host/android-goldfish.c #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr)) reg_base 125 drivers/mmc/host/android-goldfish.c void __iomem *reg_base; reg_base 463 drivers/mmc/host/android-goldfish.c host->reg_base = ioremap(res->start, resource_size(res)); reg_base 464 drivers/mmc/host/android-goldfish.c if (host->reg_base == NULL) { reg_base 521 drivers/mmc/host/android-goldfish.c iounmap(host->reg_base); reg_base 538 drivers/mmc/host/android-goldfish.c iounmap(host->reg_base); reg_base 77 drivers/mmc/host/sunxi-mmc.c readl((host)->reg_base + SDXC_##reg) reg_base 79 drivers/mmc/host/sunxi-mmc.c writel((value), (host)->reg_base + SDXC_##reg) reg_base 274 drivers/mmc/host/sunxi-mmc.c void __iomem *reg_base; reg_base 712 drivers/mmc/host/sunxi-mmc.c writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); reg_base 1276 drivers/mmc/host/sunxi-mmc.c host->reg_base = devm_ioremap_resource(&pdev->dev, reg_base 1278 drivers/mmc/host/sunxi-mmc.c if (IS_ERR(host->reg_base)) reg_base 1279 drivers/mmc/host/sunxi-mmc.c return PTR_ERR(host->reg_base); reg_base 161 drivers/mtd/nand/raw/meson_nand.c void __iomem *reg_base; reg_base 247 drivers/mtd/nand/raw/meson_nand.c writel(value, nfc->reg_base + NFC_REG_CFG); reg_base 248 drivers/mtd/nand/raw/meson_nand.c writel((1 << 31), nfc->reg_base + NFC_REG_CMD); reg_base 256 drivers/mtd/nand/raw/meson_nand.c nfc->reg_base + NFC_REG_CMD); reg_base 262 drivers/mtd/nand/raw/meson_nand.c nfc->reg_base + NFC_REG_CMD); reg_base 279 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 288 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 315 drivers/mtd/nand/raw/meson_nand.c ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size, reg_base 399 drivers/mtd/nand/raw/meson_nand.c cfg = readl(nfc->reg_base + NFC_REG_CFG); reg_base 401 drivers/mtd/nand/raw/meson_nand.c writel(cfg, nfc->reg_base + NFC_REG_CFG); reg_base 408 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 488 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 491 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 503 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 506 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 540 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 564 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 613 drivers/mtd/nand/raw/meson_nand.c nfc->reg_base + NFC_REG_CMD); reg_base 617 drivers/mtd/nand/raw/meson_nand.c writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD); reg_base 663 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 912 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 920 drivers/mtd/nand/raw/meson_nand.c writel(cmd, nfc->reg_base + NFC_REG_CMD); reg_base 1336 drivers/mtd/nand/raw/meson_nand.c cfg = readl(nfc->reg_base + NFC_REG_CFG); reg_base 1341 drivers/mtd/nand/raw/meson_nand.c writel(cfg, nfc->reg_base + NFC_REG_CFG); reg_base 1389 drivers/mtd/nand/raw/meson_nand.c nfc->reg_base = devm_ioremap_resource(dev, res); reg_base 1390 drivers/mtd/nand/raw/meson_nand.c if (IS_ERR(nfc->reg_base)) reg_base 1391 drivers/mtd/nand/raw/meson_nand.c return PTR_ERR(nfc->reg_base); reg_base 1413 drivers/mtd/nand/raw/meson_nand.c writel(0, nfc->reg_base + NFC_REG_CFG); reg_base 84 drivers/mtd/nand/raw/tango_nand.c void __iomem *reg_base; reg_base 163 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); reg_base 164 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); reg_base 165 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); reg_base 166 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); reg_base 167 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); reg_base 168 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); reg_base 208 drivers/mtd/nand/raw/tango_nand.c status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); reg_base 232 drivers/mtd/nand/raw/tango_nand.c void __iomem *addr = nfc->reg_base + NFC_STATUS; reg_base 256 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); reg_base 257 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); reg_base 258 drivers/mtd/nand/raw/tango_nand.c writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); reg_base 629 drivers/mtd/nand/raw/tango_nand.c nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 630 drivers/mtd/nand/raw/tango_nand.c if (IS_ERR(nfc->reg_base)) reg_base 631 drivers/mtd/nand/raw/tango_nand.c return PTR_ERR(nfc->reg_base); reg_base 335 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 339 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CMDCTRL); reg_base 342 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CMDCTRL); reg_base 345 drivers/mtd/spi-nor/cadence-quadspi.c ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, reg_base 363 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 378 drivers/mtd/spi-nor/cadence-quadspi.c writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); reg_base 389 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); reg_base 397 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); reg_base 411 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 433 drivers/mtd/spi-nor/cadence-quadspi.c writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); reg_base 439 drivers/mtd/spi-nor/cadence-quadspi.c writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); reg_base 451 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 459 drivers/mtd/spi-nor/cadence-quadspi.c writel(addr, reg_base + CQSPI_REG_CMDADDRESS); reg_base 468 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 483 drivers/mtd/spi-nor/cadence-quadspi.c writel(0xFF, reg_base + CQSPI_REG_MODE_BIT); reg_base 494 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_RD_INSTR); reg_base 497 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_SIZE); reg_base 500 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_SIZE); reg_base 509 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 517 drivers/mtd/spi-nor/cadence-quadspi.c writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); reg_base 518 drivers/mtd/spi-nor/cadence-quadspi.c writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); reg_base 521 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); reg_base 523 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); reg_base 527 drivers/mtd/spi-nor/cadence-quadspi.c reg_base + CQSPI_REG_INDIRECTRD); reg_base 570 drivers/mtd/spi-nor/cadence-quadspi.c ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, reg_base 579 drivers/mtd/spi-nor/cadence-quadspi.c writel(0, reg_base + CQSPI_REG_IRQMASK); reg_base 582 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); reg_base 588 drivers/mtd/spi-nor/cadence-quadspi.c writel(0, reg_base + CQSPI_REG_IRQMASK); reg_base 592 drivers/mtd/spi-nor/cadence-quadspi.c reg_base + CQSPI_REG_INDIRECTRD); reg_base 601 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 605 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_WR_INSTR); reg_base 607 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_RD_INSTR); reg_base 609 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_SIZE); reg_base 612 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_SIZE); reg_base 622 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 627 drivers/mtd/spi-nor/cadence-quadspi.c writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); reg_base 628 drivers/mtd/spi-nor/cadence-quadspi.c writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); reg_base 631 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); reg_base 633 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); reg_base 637 drivers/mtd/spi-nor/cadence-quadspi.c reg_base + CQSPI_REG_INDIRECTWR); reg_base 681 drivers/mtd/spi-nor/cadence-quadspi.c ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, reg_base 690 drivers/mtd/spi-nor/cadence-quadspi.c writel(0, reg_base + CQSPI_REG_IRQMASK); reg_base 693 drivers/mtd/spi-nor/cadence-quadspi.c writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); reg_base 701 drivers/mtd/spi-nor/cadence-quadspi.c writel(0, reg_base + CQSPI_REG_IRQMASK); reg_base 705 drivers/mtd/spi-nor/cadence-quadspi.c reg_base + CQSPI_REG_INDIRECTWR); reg_base 713 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 717 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg_base 736 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg_base 812 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 818 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg_base 821 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg_base 828 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 831 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_READCAPTURE); reg_base 844 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_READCAPTURE); reg_base 849 drivers/mtd/spi-nor/cadence-quadspi.c void __iomem *reg_base = cqspi->iobase; reg_base 852 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg_base 859 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg_base 129 drivers/net/can/at91_can.c void __iomem *reg_base; reg_base 280 drivers/net/can/at91_can.c return readl_relaxed(priv->reg_base + reg); reg_base 286 drivers/net/can/at91_can.c writel_relaxed(value, priv->reg_base + reg); reg_base 1329 drivers/net/can/at91_can.c priv->reg_base = addr; reg_base 1352 drivers/net/can/at91_can.c priv->reg_base, dev->irq); reg_base 1376 drivers/net/can/at91_can.c iounmap(priv->reg_base); reg_base 304 drivers/net/can/cc770/cc770.c priv->reg_base); reg_base 316 drivers/net/can/cc770/cc770.c priv->reg_base); reg_base 180 drivers/net/can/cc770/cc770.h void __iomem *reg_base; /* ioremap'ed address to registers */ reg_base 114 drivers/net/can/cc770/cc770_isa.c return readb(priv->reg_base + reg); reg_base 120 drivers/net/can/cc770/cc770_isa.c writeb(val, priv->reg_base + reg); reg_base 125 drivers/net/can/cc770/cc770_isa.c return inb((unsigned long)priv->reg_base + reg); reg_base 131 drivers/net/can/cc770/cc770_isa.c outb(val, (unsigned long)priv->reg_base + reg); reg_base 137 drivers/net/can/cc770/cc770_isa.c unsigned long base = (unsigned long)priv->reg_base; reg_base 152 drivers/net/can/cc770/cc770_isa.c unsigned long base = (unsigned long)priv->reg_base; reg_base 203 drivers/net/can/cc770/cc770_isa.c priv->reg_base = base; reg_base 208 drivers/net/can/cc770/cc770_isa.c priv->reg_base = (void __iomem *)port[idx]; reg_base 271 drivers/net/can/cc770/cc770_isa.c priv->reg_base, dev->irq); reg_base 295 drivers/net/can/cc770/cc770_isa.c iounmap(priv->reg_base); reg_base 61 drivers/net/can/cc770/cc770_platform.c return ioread8(priv->reg_base + reg); reg_base 67 drivers/net/can/cc770/cc770_platform.c iowrite8(val, priv->reg_base + reg); reg_base 194 drivers/net/can/cc770/cc770_platform.c priv->reg_base = base; reg_base 208 drivers/net/can/cc770/cc770_platform.c priv->reg_base, dev->irq, priv->can.clock.freq, reg_base 240 drivers/net/can/cc770/cc770_platform.c iounmap(priv->reg_base); reg_base 255 drivers/net/can/kvaser_pciefd.c void __iomem *reg_base; reg_base 268 drivers/net/can/kvaser_pciefd.c void __iomem *reg_base; reg_base 329 drivers/net/can/kvaser_pciefd.c ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, reg_base 340 drivers/net/can/kvaser_pciefd.c iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); reg_base 341 drivers/net/can/kvaser_pciefd.c iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); reg_base 342 drivers/net/can/kvaser_pciefd.c ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); reg_base 349 drivers/net/can/kvaser_pciefd.c iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); reg_base 354 drivers/net/can/kvaser_pciefd.c ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); reg_base 362 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); reg_base 367 drivers/net/can/kvaser_pciefd.c *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); reg_base 373 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); reg_base 490 drivers/net/can/kvaser_pciefd.c iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); reg_base 499 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 502 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 513 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 515 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 529 drivers/net/can/kvaser_pciefd.c iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 541 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 561 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 572 drivers/net/can/kvaser_pciefd.c iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 574 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 576 drivers/net/can/kvaser_pciefd.c status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); reg_base 583 drivers/net/can/kvaser_pciefd.c iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); reg_base 588 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 590 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 613 drivers/net/can/kvaser_pciefd.c iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 614 drivers/net/can/kvaser_pciefd.c iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 617 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 619 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 621 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 630 drivers/net/can/kvaser_pciefd.c iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 631 drivers/net/can/kvaser_pciefd.c iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 652 drivers/net/can/kvaser_pciefd.c pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); reg_base 657 drivers/net/can/kvaser_pciefd.c iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); reg_base 675 drivers/net/can/kvaser_pciefd.c iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); reg_base 681 drivers/net/can/kvaser_pciefd.c iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); reg_base 715 drivers/net/can/kvaser_pciefd.c iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 786 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); reg_base 788 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); reg_base 794 drivers/net/can/kvaser_pciefd.c iowrite32_rep(can->reg_base + reg_base 798 drivers/net/can/kvaser_pciefd.c __raw_writel(data_last, can->reg_base + reg_base 802 drivers/net/can/kvaser_pciefd.c __raw_writel(0, can->reg_base + reg_base 806 drivers/net/can/kvaser_pciefd.c count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG); reg_base 839 drivers/net/can/kvaser_pciefd.c mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 843 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 846 drivers/net/can/kvaser_pciefd.c ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG, reg_base 856 drivers/net/can/kvaser_pciefd.c iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG); reg_base 858 drivers/net/can/kvaser_pciefd.c iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG); reg_base 861 drivers/net/can/kvaser_pciefd.c iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); reg_base 936 drivers/net/can/kvaser_pciefd.c can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE + reg_base 950 drivers/net/can/kvaser_pciefd.c tx_npackets = ioread32(can->reg_base + reg_base 980 drivers/net/can/kvaser_pciefd.c status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); reg_base 996 drivers/net/can/kvaser_pciefd.c iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 999 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 1040 drivers/net/can/kvaser_pciefd.c iowrite32(word1, pcie->reg_base + offset); reg_base 1041 drivers/net/can/kvaser_pciefd.c iowrite32(word2, pcie->reg_base + offset + 4); reg_base 1051 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); reg_base 1073 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); reg_base 1075 drivers/net/can/kvaser_pciefd.c srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); reg_base 1083 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); reg_base 1098 drivers/net/can/kvaser_pciefd.c sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG); reg_base 1111 drivers/net/can/kvaser_pciefd.c build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG); reg_base 1117 drivers/net/can/kvaser_pciefd.c srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); reg_base 1124 drivers/net/can/kvaser_pciefd.c pcie->bus_freq = ioread32(pcie->reg_base + reg_base 1126 drivers/net/can/kvaser_pciefd.c pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG); reg_base 1132 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG); reg_base 1398 drivers/net/can/kvaser_pciefd.c status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); reg_base 1410 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 1413 drivers/net/can/kvaser_pciefd.c iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); reg_base 1416 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 1422 drivers/net/can/kvaser_pciefd.c u8 count = ioread32(can->reg_base + reg_base 1427 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); reg_base 1460 drivers/net/can/kvaser_pciefd.c u8 count = ioread32(can->reg_base + reg_base 1465 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); reg_base 1535 drivers/net/can/kvaser_pciefd.c u8 count = ioread32(can->reg_base + reg_base 1673 drivers/net/can/kvaser_pciefd.c irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); reg_base 1678 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); reg_base 1685 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); reg_base 1694 drivers/net/can/kvaser_pciefd.c iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); reg_base 1700 drivers/net/can/kvaser_pciefd.c u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 1706 drivers/net/can/kvaser_pciefd.c u8 count = ioread32(can->reg_base + reg_base 1711 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); reg_base 1724 drivers/net/can/kvaser_pciefd.c iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); reg_base 1734 drivers/net/can/kvaser_pciefd.c board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG); reg_base 1754 drivers/net/can/kvaser_pciefd.c iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG); reg_base 1767 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 1795 drivers/net/can/kvaser_pciefd.c pcie->reg_base = pci_iomap(pdev, 0, 0); reg_base 1796 drivers/net/can/kvaser_pciefd.c if (!pcie->reg_base) { reg_base 1816 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); reg_base 1821 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG); reg_base 1825 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_IRQ_REG); reg_base 1827 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_IEN_REG); reg_base 1831 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); reg_base 1833 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); reg_base 1851 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); reg_base 1855 drivers/net/can/kvaser_pciefd.c pci_iounmap(pdev, pcie->reg_base); reg_base 1875 drivers/net/can/kvaser_pciefd.c can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); reg_base 1891 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); reg_base 1893 drivers/net/can/kvaser_pciefd.c pcie->reg_base + KVASER_PCIEFD_IRQ_REG); reg_base 1894 drivers/net/can/kvaser_pciefd.c iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG); reg_base 1899 drivers/net/can/kvaser_pciefd.c pci_iounmap(pdev, pcie->reg_base); reg_base 317 drivers/net/can/mscan/mpc5xxx_can.c priv->reg_base = base; reg_base 339 drivers/net/can/mscan/mpc5xxx_can.c priv->reg_base, dev->irq, priv->can.clock.freq); reg_base 366 drivers/net/can/mscan/mpc5xxx_can.c iounmap(priv->reg_base); reg_base 379 drivers/net/can/mscan/mpc5xxx_can.c struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; reg_base 390 drivers/net/can/mscan/mpc5xxx_can.c struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; reg_base 53 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 129 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 169 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 190 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 295 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 336 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 382 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 428 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 508 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 529 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 541 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 598 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 627 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 666 drivers/net/can/mscan/mscan.c struct mscan_regs __iomem *regs = priv->reg_base; reg_base 274 drivers/net/can/mscan/mscan.h void __iomem *reg_base; /* ioremap'ed address to registers */ reg_base 173 drivers/net/can/peak_canfd/peak_pciefd_main.c void __iomem *reg_base; /* channel config base addr */ reg_base 194 drivers/net/can/peak_canfd/peak_pciefd_main.c void __iomem *reg_base; reg_base 217 drivers/net/can/peak_canfd/peak_pciefd_main.c return readl(priv->reg_base + reg); reg_base 224 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); reg_base 230 drivers/net/can/peak_canfd/peak_pciefd_main.c return readl(priv->reg_base + reg); reg_base 237 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); reg_base 612 drivers/net/can/peak_canfd/peak_pciefd_main.c priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index); reg_base 686 drivers/net/can/peak_canfd/peak_pciefd_main.c ndev->name, priv->reg_base, ndev->irq); reg_base 763 drivers/net/can/peak_canfd/peak_pciefd_main.c pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE); reg_base 764 drivers/net/can/peak_canfd/peak_pciefd_main.c if (!pciefd->reg_base) { reg_base 834 drivers/net/can/peak_canfd/peak_pciefd_main.c pci_iounmap(pdev, pciefd->reg_base); reg_base 856 drivers/net/can/peak_canfd/peak_pciefd_main.c pci_iounmap(pdev, pciefd->reg_base); reg_base 114 drivers/net/can/sja1000/ems_pci.c return readb(priv->reg_base + (port * 4)); reg_base 120 drivers/net/can/sja1000/ems_pci.c writeb(val, priv->reg_base + (port * 4)); reg_base 134 drivers/net/can/sja1000/ems_pci.c return readb(priv->reg_base + port); reg_base 140 drivers/net/can/sja1000/ems_pci.c writeb(val, priv->reg_base + port); reg_base 296 drivers/net/can/sja1000/ems_pci.c priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET reg_base 338 drivers/net/can/sja1000/ems_pci.c i + 1, priv->reg_base, dev->irq); reg_base 73 drivers/net/can/sja1000/ems_pcmcia.c return readb(priv->reg_base + port); reg_base 79 drivers/net/can/sja1000/ems_pcmcia.c writeb(val, priv->reg_base + port); reg_base 210 drivers/net/can/sja1000/ems_pcmcia.c priv->reg_base = card->base_addr + EMS_PCMCIA_CAN_BASE_OFFSET + reg_base 233 drivers/net/can/sja1000/ems_pcmcia.c i, priv->reg_base, dev->irq); reg_base 58 drivers/net/can/sja1000/f81601.c return readb(priv->reg_base + port); reg_base 68 drivers/net/can/sja1000/f81601.c writeb(val, priv->reg_base + port); reg_base 69 drivers/net/can/sja1000/f81601.c readb(priv->reg_base); reg_base 160 drivers/net/can/sja1000/f81601.c priv->reg_base = card->addr + 0x80 * i; reg_base 188 drivers/net/can/sja1000/f81601.c dev->name, priv->reg_base, dev->irq); reg_base 109 drivers/net/can/sja1000/kvaser_pci.c return ioread8(priv->reg_base + port); reg_base 115 drivers/net/can/sja1000/kvaser_pci.c iowrite8(val, priv->reg_base + port); reg_base 190 drivers/net/can/sja1000/kvaser_pci.c pci_iounmap(board->pci_dev, priv->reg_base); reg_base 242 drivers/net/can/sja1000/kvaser_pci.c priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES; reg_base 256 drivers/net/can/sja1000/kvaser_pci.c priv->reg_base, board->conf_addr, dev->irq); reg_base 143 drivers/net/can/sja1000/peak_pci.c void __iomem *reg_base; /* first channel base address */ reg_base 398 drivers/net/can/sja1000/peak_pci.c int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; reg_base 453 drivers/net/can/sja1000/peak_pci.c card->reg_base = priv->reg_base; reg_base 526 drivers/net/can/sja1000/peak_pci.c return readb(priv->reg_base + (port << 2)); reg_base 532 drivers/net/can/sja1000/peak_pci.c writeb(val, priv->reg_base + (port << 2)); reg_base 551 drivers/net/can/sja1000/peak_pci.c void __iomem *cfg_base, *reg_base; reg_base 590 drivers/net/can/sja1000/peak_pci.c reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); reg_base 591 drivers/net/can/sja1000/peak_pci.c if (!reg_base) { reg_base 620 drivers/net/can/sja1000/peak_pci.c priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; reg_base 671 drivers/net/can/sja1000/peak_pci.c dev->name, priv->reg_base, chan->cfg_base, dev->irq); reg_base 701 drivers/net/can/sja1000/peak_pci.c pci_iounmap(pdev, reg_base); reg_base 724 drivers/net/can/sja1000/peak_pci.c void __iomem *reg_base = priv->reg_base; reg_base 748 drivers/net/can/sja1000/peak_pci.c pci_iounmap(pdev, reg_base); reg_base 179 drivers/net/can/sja1000/peak_pcmcia.c return ioread8(priv->reg_base + port); reg_base 188 drivers/net/can/sja1000/peak_pcmcia.c int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE; reg_base 206 drivers/net/can/sja1000/peak_pcmcia.c iowrite8(v, priv->reg_base + port); reg_base 549 drivers/net/can/sja1000/peak_pcmcia.c priv->reg_base = card->ioport_addr + PCC_CHAN_OFF(i); reg_base 585 drivers/net/can/sja1000/peak_pcmcia.c netdev->name, i, priv->reg_base, pdev->irq); reg_base 411 drivers/net/can/sja1000/plx_pci.c return ioread8(priv->reg_base + port); reg_base 416 drivers/net/can/sja1000/plx_pci.c iowrite8(val, priv->reg_base + port); reg_base 594 drivers/net/can/sja1000/plx_pci.c if (priv->reg_base) reg_base 595 drivers/net/can/sja1000/plx_pci.c pci_iounmap(pdev, priv->reg_base); reg_base 696 drivers/net/can/sja1000/plx_pci.c priv->reg_base = addr + cm->offset; reg_base 720 drivers/net/can/sja1000/plx_pci.c "registered as %s\n", i + 1, priv->reg_base, reg_base 108 drivers/net/can/sja1000/sja1000.c if (priv->reg_base && sja1000_is_absent(priv)) { reg_base 166 drivers/net/can/sja1000/sja1000.h void __iomem *reg_base; /* ioremap'ed address to registers */ reg_base 71 drivers/net/can/sja1000/sja1000_isa.c return readb(priv->reg_base + reg); reg_base 77 drivers/net/can/sja1000/sja1000_isa.c writeb(val, priv->reg_base + reg); reg_base 82 drivers/net/can/sja1000/sja1000_isa.c return inb((unsigned long)priv->reg_base + reg); reg_base 88 drivers/net/can/sja1000/sja1000_isa.c outb(val, (unsigned long)priv->reg_base + reg); reg_base 94 drivers/net/can/sja1000/sja1000_isa.c unsigned long flags, base = (unsigned long)priv->reg_base; reg_base 108 drivers/net/can/sja1000/sja1000_isa.c unsigned long flags, base = (unsigned long)priv->reg_base; reg_base 158 drivers/net/can/sja1000/sja1000_isa.c priv->reg_base = base; reg_base 163 drivers/net/can/sja1000/sja1000_isa.c priv->reg_base = (void __iomem *)port[idx]; reg_base 209 drivers/net/can/sja1000/sja1000_isa.c DRV_NAME, priv->reg_base, dev->irq); reg_base 233 drivers/net/can/sja1000/sja1000_isa.c iounmap(priv->reg_base); reg_base 44 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg); reg_base 49 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg); reg_base 54 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg * 2); reg_base 59 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 2); reg_base 64 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg * 4); reg_base 69 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 4); reg_base 79 drivers/net/can/sja1000/sja1000_platform.c iowrite16(reg, priv->reg_base + 0); reg_base 80 drivers/net/can/sja1000/sja1000_platform.c val = ioread16(priv->reg_base + 2); reg_base 93 drivers/net/can/sja1000/sja1000_platform.c iowrite16(reg, priv->reg_base + 0); reg_base 94 drivers/net/can/sja1000/sja1000_platform.c iowrite16(val, priv->reg_base + 2); reg_base 266 drivers/net/can/sja1000/sja1000_platform.c priv->reg_base = addr; reg_base 291 drivers/net/can/sja1000/sja1000_platform.c DRV_NAME, priv->reg_base, dev->irq); reg_base 69 drivers/net/can/sja1000/tscan1.c return inb((unsigned long)priv->reg_base + reg); reg_base 75 drivers/net/can/sja1000/tscan1.c outb(val, (unsigned long)priv->reg_base + reg); reg_base 141 drivers/net/can/sja1000/tscan1.c priv->reg_base = (void __iomem *)sja1000_base; reg_base 174 drivers/net/can/sja1000/tscan1.c sja1000_base = (unsigned long)priv->reg_base; reg_base 208 drivers/net/can/xilinx_can.c void __iomem *reg_base; reg_base 291 drivers/net/can/xilinx_can.c iowrite32(val, priv->reg_base + reg); reg_base 304 drivers/net/can/xilinx_can.c return ioread32(priv->reg_base + reg); reg_base 318 drivers/net/can/xilinx_can.c iowrite32be(val, priv->reg_base + reg); reg_base 331 drivers/net/can/xilinx_can.c return ioread32be(priv->reg_base + reg); reg_base 1749 drivers/net/can/xilinx_can.c priv->reg_base = addr; reg_base 1814 drivers/net/can/xilinx_can.c priv->reg_base, ndev->irq, priv->can.clock.freq, reg_base 7065 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg_base = 0xffffffff; reg_base 7074 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (reg_base == 0xffffffff) reg_base 7075 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_base = reg & BNXT_GRC_BASE_MASK; reg_base 7076 drivers/net/ethernet/broadcom/bnxt/bnxt.c if ((reg & BNXT_GRC_BASE_MASK) != reg_base) reg_base 7081 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (reg_base == 0xffffffff) reg_base 7084 drivers/net/ethernet/broadcom/bnxt/bnxt.c writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + reg_base 1408 drivers/net/ethernet/broadcom/bnxt/bnxt.h u32 reg_base; reg_base 126 drivers/net/ethernet/cavium/common/cavium_ptp.c writeq(comp, clock->reg_base + PTP_CLOCK_COMP); reg_base 214 drivers/net/ethernet/cavium/common/cavium_ptp.c return readq(clock->reg_base + PTP_CLOCK_HI); reg_base 243 drivers/net/ethernet/cavium/common/cavium_ptp.c clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; reg_base 272 drivers/net/ethernet/cavium/common/cavium_ptp.c clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); reg_base 274 drivers/net/ethernet/cavium/common/cavium_ptp.c writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); reg_base 277 drivers/net/ethernet/cavium/common/cavium_ptp.c writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); reg_base 289 drivers/net/ethernet/cavium/common/cavium_ptp.c clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); reg_base 291 drivers/net/ethernet/cavium/common/cavium_ptp.c writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); reg_base 318 drivers/net/ethernet/cavium/common/cavium_ptp.c clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); reg_base 320 drivers/net/ethernet/cavium/common/cavium_ptp.c writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); reg_base 19 drivers/net/ethernet/cavium/common/cavium_ptp.h void __iomem *reg_base; reg_base 280 drivers/net/ethernet/cavium/thunder/nic.h void __iomem *reg_base; reg_base 46 drivers/net/ethernet/cavium/thunder/nic_main.c void __iomem *reg_base; /* Register start address */ reg_base 90 drivers/net/ethernet/cavium/thunder/nic_main.c writeq_relaxed(val, nic->reg_base + offset); reg_base 95 drivers/net/ethernet/cavium/thunder/nic_main.c return readq_relaxed(nic->reg_base + offset); reg_base 135 drivers/net/ethernet/cavium/thunder/nic_main.c void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf); reg_base 1338 drivers/net/ethernet/cavium/thunder/nic_main.c nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); reg_base 1339 drivers/net/ethernet/cavium/thunder/nic_main.c if (!nic->reg_base) { reg_base 95 drivers/net/ethernet/cavium/thunder/nicvf_main.c writeq_relaxed(val, nic->reg_base + offset); reg_base 100 drivers/net/ethernet/cavium/thunder/nicvf_main.c return readq_relaxed(nic->reg_base + offset); reg_base 106 drivers/net/ethernet/cavium/thunder/nicvf_main.c void __iomem *addr = nic->reg_base + offset; reg_base 113 drivers/net/ethernet/cavium/thunder/nicvf_main.c void __iomem *addr = nic->reg_base + offset; reg_base 2189 drivers/net/ethernet/cavium/thunder/nicvf_main.c nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); reg_base 2190 drivers/net/ethernet/cavium/thunder/nicvf_main.c if (!nic->reg_base) { reg_base 73 drivers/net/ethernet/cavium/thunder/thunder_bgx.c void __iomem *reg_base; reg_base 109 drivers/net/ethernet/cavium/thunder/thunder_bgx.c void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; reg_base 116 drivers/net/ethernet/cavium/thunder/thunder_bgx.c void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; reg_base 123 drivers/net/ethernet/cavium/thunder/thunder_bgx.c void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset; reg_base 1618 drivers/net/ethernet/cavium/thunder/thunder_bgx.c bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); reg_base 1619 drivers/net/ethernet/cavium/thunder/thunder_bgx.c if (!bgx->reg_base) { reg_base 47 drivers/net/ethernet/cavium/thunder/thunder_xcv.c void __iomem *reg_base; reg_base 70 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 72 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 75 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 77 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 84 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); reg_base 87 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); reg_base 92 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 94 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 95 drivers/net/ethernet/cavium/thunder/thunder_xcv.c readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 100 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 102 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 104 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 106 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 127 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_CTL); reg_base 130 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); reg_base 133 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 135 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 138 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 140 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 143 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET); reg_base 146 drivers/net/ethernet/cavium/thunder/thunder_xcv.c cfg = readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 148 drivers/net/ethernet/cavium/thunder/thunder_xcv.c writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); reg_base 149 drivers/net/ethernet/cavium/thunder/thunder_xcv.c readq_relaxed(xcv->reg_base + XCV_RESET); reg_base 179 drivers/net/ethernet/cavium/thunder/thunder_xcv.c xcv->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); reg_base 180 drivers/net/ethernet/cavium/thunder/thunder_xcv.c if (!xcv->reg_base) { reg_base 32 drivers/net/ethernet/marvell/mvneta_bm.c writel(data, priv->reg_base + offset); reg_base 37 drivers/net/ethernet/marvell/mvneta_bm.c return readl(priv->reg_base + offset); reg_base 420 drivers/net/ethernet/marvell/mvneta_bm.c priv->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 421 drivers/net/ethernet/marvell/mvneta_bm.c if (IS_ERR(priv->reg_base)) reg_base 422 drivers/net/ethernet/marvell/mvneta_bm.c return PTR_ERR(priv->reg_base); reg_base 96 drivers/net/ethernet/marvell/mvneta_bm.h void __iomem *reg_base; reg_base 55 drivers/net/ethernet/marvell/octeontx2/af/cgx.c void __iomem *reg_base; reg_base 86 drivers/net/ethernet/marvell/octeontx2/af/cgx.c writeq(val, cgx->reg_base + (lmac << 18) + offset); reg_base 91 drivers/net/ethernet/marvell/octeontx2/af/cgx.c return readq(cgx->reg_base + (lmac << 18) + offset); reg_base 804 drivers/net/ethernet/marvell/octeontx2/af/cgx.c cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); reg_base 805 drivers/net/ethernet/marvell/octeontx2/af/cgx.c if (!cgx->reg_base) { reg_base 39 drivers/net/ethernet/marvell/octeontx2/af/mbox.c mbox->reg_base = NULL; reg_base 48 drivers/net/ethernet/marvell/octeontx2/af/mbox.c void *reg_base, int direction, int ndevs) reg_base 111 drivers/net/ethernet/marvell/octeontx2/af/mbox.c mbox->reg_base = reg_base; reg_base 191 drivers/net/ethernet/marvell/octeontx2/af/mbox.c writeq(1, (void __iomem *)mbox->reg_base + reg_base 65 drivers/net/ethernet/marvell/octeontx2/af/mbox.h void *reg_base;/* CSR base for this dev */ reg_base 97 drivers/net/ethernet/marvell/octeontx2/af/mbox.h struct pci_dev *pdev, void __force *reg_base, reg_base 1586 drivers/net/ethernet/marvell/octeontx2/af/rvu.c void __iomem *hwbase = NULL, *reg_base; reg_base 1598 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_base = rvu->afreg_base; reg_base 1605 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_base = rvu->pfreg_base; reg_base 1642 drivers/net/ethernet/marvell/octeontx2/af/rvu.c err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); reg_base 1647 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_base, dir_up, num); reg_base 6921 drivers/net/ethernet/micrel/ksz884x.c unsigned long reg_base; reg_base 6942 drivers/net/ethernet/micrel/ksz884x.c reg_base = pci_resource_start(pdev, 0); reg_base 6947 drivers/net/ethernet/micrel/ksz884x.c if (!request_mem_region(reg_base, reg_len, DRV_NAME)) reg_base 6962 drivers/net/ethernet/micrel/ksz884x.c hw->io = ioremap(reg_base, reg_len); reg_base 7133 drivers/net/ethernet/micrel/ksz884x.c release_mem_region(reg_base, reg_len); reg_base 461 drivers/net/ethernet/sfc/falcon/qt202x_phy.c int mmd, reg_base, rc, i; reg_base 465 drivers/net/ethernet/sfc/falcon/qt202x_phy.c reg_base = 0xd000; reg_base 468 drivers/net/ethernet/sfc/falcon/qt202x_phy.c reg_base = 0x8007; reg_base 472 drivers/net/ethernet/sfc/falcon/qt202x_phy.c rc = ef4_mdio_read(efx, mmd, reg_base + ee->offset + i); reg_base 419 drivers/net/wireless/ath/ath9k/hw.h #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) reg_base 46 drivers/nvmem/lpc18xx_eeprom.c void __iomem *reg_base; reg_base 57 drivers/nvmem/lpc18xx_eeprom.c writel(val, eeprom->reg_base + reg); reg_base 63 drivers/nvmem/lpc18xx_eeprom.c return readl(eeprom->reg_base + reg); reg_base 176 drivers/nvmem/lpc18xx_eeprom.c eeprom->reg_base = devm_ioremap_resource(dev, res); reg_base 177 drivers/nvmem/lpc18xx_eeprom.c if (IS_ERR(eeprom->reg_base)) reg_base 178 drivers/nvmem/lpc18xx_eeprom.c return PTR_ERR(eeprom->reg_base); reg_base 66 drivers/pci/controller/dwc/pcie-hisi.c void __iomem *reg_base = cfg->priv; reg_base 69 drivers/pci/controller/dwc/pcie-hisi.c return reg_base + where; reg_base 82 drivers/pci/controller/dwc/pcie-hisi.c void __iomem *reg_base; reg_base 99 drivers/pci/controller/dwc/pcie-hisi.c reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res)); reg_base 100 drivers/pci/controller/dwc/pcie-hisi.c if (!reg_base) reg_base 103 drivers/pci/controller/dwc/pcie-hisi.c cfg->priv = reg_base; reg_base 349 drivers/pci/controller/dwc/pcie-hisi.c void __iomem *reg_base; reg_base 357 drivers/pci/controller/dwc/pcie-hisi.c reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res)); reg_base 358 drivers/pci/controller/dwc/pcie-hisi.c if (!reg_base) reg_base 361 drivers/pci/controller/dwc/pcie-hisi.c cfg->priv = reg_base; reg_base 452 drivers/pci/controller/pcie-cadence-ep.c pcie->reg_base = devm_ioremap_resource(dev, res); reg_base 453 drivers/pci/controller/pcie-cadence-ep.c if (IS_ERR(pcie->reg_base)) { reg_base 455 drivers/pci/controller/pcie-cadence-ep.c return PTR_ERR(pcie->reg_base); reg_base 59 drivers/pci/controller/pcie-cadence-host.c return pcie->reg_base + (where & 0xfff); reg_base 271 drivers/pci/controller/pcie-cadence-host.c pcie->reg_base = devm_ioremap_resource(dev, res); reg_base 272 drivers/pci/controller/pcie-cadence-host.c if (IS_ERR(pcie->reg_base)) { reg_base 274 drivers/pci/controller/pcie-cadence-host.c return PTR_ERR(pcie->reg_base); reg_base 232 drivers/pci/controller/pcie-cadence.h void __iomem *reg_base; reg_base 244 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + reg); reg_base 249 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + reg); reg_base 254 drivers/pci/controller/pcie-cadence.h writel(value, pcie->reg_base + reg); reg_base 259 drivers/pci/controller/pcie-cadence.h return readl(pcie->reg_base + reg); reg_base 266 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); reg_base 272 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); reg_base 279 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 285 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 291 drivers/pci/controller/pcie-cadence.h writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 296 drivers/pci/controller/pcie-cadence.h return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 301 drivers/pci/controller/pcie-cadence.h return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 306 drivers/pci/controller/pcie-cadence.h return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg_base 181 drivers/pci/controller/pcie-rockchip-host.c *val = readl(rockchip->reg_base + busdev); reg_base 183 drivers/pci/controller/pcie-rockchip-host.c *val = readw(rockchip->reg_base + busdev); reg_base 185 drivers/pci/controller/pcie-rockchip-host.c *val = readb(rockchip->reg_base + busdev); reg_base 212 drivers/pci/controller/pcie-rockchip-host.c writel(val, rockchip->reg_base + busdev); reg_base 214 drivers/pci/controller/pcie-rockchip-host.c writew(val, rockchip->reg_base + busdev); reg_base 216 drivers/pci/controller/pcie-rockchip-host.c writeb(val, rockchip->reg_base + busdev); reg_base 37 drivers/pci/controller/pcie-rockchip.c rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); reg_base 38 drivers/pci/controller/pcie-rockchip.c if (IS_ERR(rockchip->reg_base)) reg_base 39 drivers/pci/controller/pcie-rockchip.c return PTR_ERR(rockchip->reg_base); reg_base 279 drivers/pci/controller/pcie-rockchip.h void __iomem *reg_base; /* DT axi-base */ reg_base 108 drivers/pci/controller/pcie-xilinx.c void __iomem *reg_base; reg_base 122 drivers/pci/controller/pcie-xilinx.c return readl(port->reg_base + reg); reg_base 127 drivers/pci/controller/pcie-xilinx.c writel(val, port->reg_base + reg); reg_base 197 drivers/pci/controller/pcie-xilinx.c return port->reg_base + relbus + where; reg_base 593 drivers/pci/controller/pcie-xilinx.c port->reg_base = devm_pci_remap_cfg_resource(dev, ®s); reg_base 594 drivers/pci/controller/pcie-xilinx.c if (IS_ERR(port->reg_base)) reg_base 595 drivers/pci/controller/pcie-xilinx.c return PTR_ERR(port->reg_base); reg_base 111 drivers/perf/arm_smmuv3_pmu.c void __iomem *reg_base; reg_base 137 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); reg_base 138 drivers/perf/arm_smmuv3_pmu.c writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR); reg_base 145 drivers/perf/arm_smmuv3_pmu.c writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR); reg_base 146 drivers/perf/arm_smmuv3_pmu.c writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); reg_base 172 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0); reg_base 177 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); reg_base 182 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0); reg_base 188 drivers/perf/arm_smmuv3_pmu.c writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); reg_base 194 drivers/perf/arm_smmuv3_pmu.c writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx)); reg_base 199 drivers/perf/arm_smmuv3_pmu.c writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx)); reg_base 649 drivers/perf/arm_smmuv3_pmu.c writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); reg_base 650 drivers/perf/arm_smmuv3_pmu.c writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); reg_base 652 drivers/perf/arm_smmuv3_pmu.c pmu->reg_base + SMMU_PMCG_IRQ_CFG2); reg_base 662 drivers/perf/arm_smmuv3_pmu.c writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); reg_base 665 drivers/perf/arm_smmuv3_pmu.c if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) reg_base 704 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); reg_base 706 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); reg_base 759 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->reg_base = devm_ioremap_resource(dev, res_0); reg_base 760 drivers/perf/arm_smmuv3_pmu.c if (IS_ERR(smmu_pmu->reg_base)) reg_base 761 drivers/perf/arm_smmuv3_pmu.c return PTR_ERR(smmu_pmu->reg_base); reg_base 763 drivers/perf/arm_smmuv3_pmu.c cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); reg_base 772 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->reloc_base = smmu_pmu->reg_base; reg_base 779 drivers/perf/arm_smmuv3_pmu.c ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0); reg_base 780 drivers/perf/arm_smmuv3_pmu.c ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1); reg_base 80 drivers/phy/rockchip/phy-rockchip-emmc.c struct regmap *reg_base; reg_base 98 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 103 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 156 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 169 drivers/phy/rockchip/phy-rockchip-emmc.c ret = regmap_read_poll_timeout(rk_phy->reg_base, reg_base 179 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 185 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 217 drivers/phy/rockchip/phy-rockchip-emmc.c ret = regmap_read_poll_timeout(rk_phy->reg_base, reg_base 278 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 285 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 292 drivers/phy/rockchip/phy-rockchip-emmc.c regmap_write(rk_phy->reg_base, reg_base 360 drivers/phy/rockchip/phy-rockchip-emmc.c rk_phy->reg_base = grf; reg_base 67 drivers/phy/rockchip/phy-rockchip-pcie.c struct regmap *reg_base; reg_base 103 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 111 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 116 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 127 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 131 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_read(rk_phy->reg_base, reg_base 145 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, reg_base 166 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, reg_base 194 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 199 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, reg_base 214 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_read(rk_phy->reg_base, reg_base 235 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_read(rk_phy->reg_base, reg_base 251 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, reg_base 257 drivers/phy/rockchip/phy-rockchip-pcie.c regmap_read(rk_phy->reg_base, reg_base 387 drivers/phy/rockchip/phy-rockchip-pcie.c rk_phy->reg_base = grf; reg_base 63 drivers/phy/rockchip/phy-rockchip-usb.c struct regmap *reg_base; reg_base 85 drivers/phy/rockchip/phy-rockchip-usb.c return regmap_write(phy->base->reg_base, phy->reg_offset, val); reg_base 125 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); reg_base 478 drivers/phy/rockchip/phy-rockchip-usb.c phy_base->reg_base = ERR_PTR(-ENODEV); reg_base 480 drivers/phy/rockchip/phy-rockchip-usb.c phy_base->reg_base = syscon_node_to_regmap( reg_base 482 drivers/phy/rockchip/phy-rockchip-usb.c if (IS_ERR(phy_base->reg_base)) reg_base 483 drivers/phy/rockchip/phy-rockchip-usb.c phy_base->reg_base = syscon_regmap_lookup_by_phandle( reg_base 485 drivers/phy/rockchip/phy-rockchip-usb.c if (IS_ERR(phy_base->reg_base)) { reg_base 487 drivers/phy/rockchip/phy-rockchip-usb.c return PTR_ERR(phy_base->reg_base); reg_base 90 drivers/pinctrl/bcm/pinctrl-bcm281xx.c void __iomem *reg_base; reg_base 1408 drivers/pinctrl/bcm/pinctrl-bcm281xx.c pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 1409 drivers/pinctrl/bcm/pinctrl-bcm281xx.c if (IS_ERR(pdata->reg_base)) { reg_base 1415 drivers/pinctrl/bcm/pinctrl-bcm281xx.c pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, reg_base 392 drivers/pinctrl/pinctrl-artpec6.c unsigned int reg_base; reg_base 413 drivers/pinctrl/pinctrl-artpec6.c pin_register[i].reg_base; reg_base 113 drivers/pinctrl/pinctrl-at91-pio4.c void __iomem *reg_base; reg_base 146 drivers/pinctrl/pinctrl-at91-pio4.c return readl_relaxed(atmel_pioctrl->reg_base reg_base 154 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(val, atmel_pioctrl->reg_base reg_base 377 drivers/pinctrl/pinctrl-at91-pio4.c void __iomem *addr = atmel_pioctrl->reg_base reg_base 393 drivers/pinctrl/pinctrl-at91-pio4.c void __iomem *addr = atmel_pioctrl->reg_base reg_base 773 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(mask, atmel_pioctrl->reg_base + reg_base 777 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(mask, atmel_pioctrl->reg_base + reg_base 959 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); reg_base 960 drivers/pinctrl/pinctrl-at91-pio4.c if (IS_ERR(atmel_pioctrl->reg_base)) reg_base 91 drivers/pinctrl/pinctrl-ingenic.c unsigned int irq, reg_base; reg_base 1337 drivers/pinctrl/pinctrl-ingenic.c regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); reg_base 1350 drivers/pinctrl/pinctrl-ingenic.c regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); reg_base 1957 drivers/pinctrl/pinctrl-ingenic.c jzgc->reg_base = bank * 0x100; reg_base 81 drivers/pinctrl/pinctrl-oxnas.c void __iomem *reg_base; reg_base 759 drivers/pinctrl/pinctrl-oxnas.c return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask); reg_base 768 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); reg_base 778 drivers/pinctrl/pinctrl-oxnas.c return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; reg_base 788 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_SET); reg_base 790 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); reg_base 800 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); reg_base 987 drivers/pinctrl/pinctrl-oxnas.c writel(mask, bank->reg_base + IRQ_PENDING); reg_base 998 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, reg_base 999 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + RE_IRQ_ENABLE); reg_base 1002 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, reg_base 1003 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + FE_IRQ_ENABLE); reg_base 1014 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, reg_base 1015 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + RE_IRQ_ENABLE); reg_base 1018 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, reg_base 1019 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + FE_IRQ_ENABLE); reg_base 1052 drivers/pinctrl/pinctrl-oxnas.c stat = readl(bank->reg_base + IRQ_PENDING); reg_base 1223 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 1224 drivers/pinctrl/pinctrl-oxnas.c if (IS_ERR(bank->reg_base)) reg_base 1225 drivers/pinctrl/pinctrl-oxnas.c return PTR_ERR(bank->reg_base); reg_base 62 drivers/pinctrl/pinctrl-pic32.c void __iomem *reg_base; reg_base 69 drivers/pinctrl/pinctrl-pic32.c void __iomem *reg_base; reg_base 1784 drivers/pinctrl/pinctrl-pic32.c writel(functions->muxval, pctl->reg_base + functions->muxreg); reg_base 1808 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); reg_base 1819 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); reg_base 1828 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); reg_base 1838 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); reg_base 1840 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); reg_base 1850 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); reg_base 1889 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPU_REG) & mask); reg_base 1892 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPD_REG) & mask); reg_base 1895 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + ANSEL_REG) & mask); reg_base 1898 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); reg_base 1901 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ODCU_REG) & mask); reg_base 1904 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + TRIS_REG) & mask); reg_base 1907 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + TRIS_REG) & mask); reg_base 1940 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); reg_base 1944 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); reg_base 1948 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); reg_base 1952 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); reg_base 1956 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); reg_base 1993 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset)); reg_base 2000 drivers/pinctrl/pinctrl-pic32.c writel(0, bank->reg_base + CNF_REG); reg_base 2007 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); reg_base 2014 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); reg_base 2035 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); reg_base 2037 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); reg_base 2039 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); reg_base 2043 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); reg_base 2045 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); reg_base 2047 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); reg_base 2051 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); reg_base 2053 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); reg_base 2055 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); reg_base 2073 drivers/pinctrl/pinctrl-pic32.c cnen_rise = readl(bank->reg_base + CNEN_REG); reg_base 2074 drivers/pinctrl/pinctrl-pic32.c cnne_fall = readl(bank->reg_base + CNNE_REG); reg_base 2097 drivers/pinctrl/pinctrl-pic32.c stat = readl(bank->reg_base + CNF_REG); reg_base 2158 drivers/pinctrl/pinctrl-pic32.c pctl->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 2159 drivers/pinctrl/pinctrl-pic32.c if (IS_ERR(pctl->reg_base)) reg_base 2160 drivers/pinctrl/pinctrl-pic32.c return PTR_ERR(pctl->reg_base); reg_base 2220 drivers/pinctrl/pinctrl-pic32.c bank->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 2221 drivers/pinctrl/pinctrl-pic32.c if (IS_ERR(bank->reg_base)) reg_base 2222 drivers/pinctrl/pinctrl-pic32.c return PTR_ERR(bank->reg_base); reg_base 142 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg_base; reg_base 2211 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); reg_base 2239 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); reg_base 2245 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); reg_base 2693 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; reg_base 2720 drivers/pinctrl/pinctrl-rockchip.c data = readl(bank->reg_base + GPIO_EXT_PORT); reg_base 2753 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; reg_base 2845 drivers/pinctrl/pinctrl-rockchip.c pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); reg_base 2869 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); reg_base 2873 drivers/pinctrl/pinctrl-rockchip.c polarity = readl_relaxed(bank->reg_base + reg_base 2880 drivers/pinctrl/pinctrl-rockchip.c bank->reg_base + GPIO_INT_POLARITY); reg_base 2885 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + reg_base 2915 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); reg_base 2917 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); reg_base 2929 drivers/pinctrl/pinctrl-rockchip.c level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); reg_base 2930 drivers/pinctrl/pinctrl-rockchip.c polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); reg_base 2941 drivers/pinctrl/pinctrl-rockchip.c data = readl(bank->reg_base + GPIO_EXT_PORT); reg_base 2974 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); reg_base 2975 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); reg_base 3072 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); reg_base 3073 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); reg_base 3076 drivers/pinctrl/pinctrl-rockchip.c gc->reg_base = bank->reg_base; reg_base 3177 drivers/pinctrl/pinctrl-rockchip.c bank->reg_base = devm_ioremap_resource(info->dev, &res); reg_base 3178 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(bank->reg_base)) reg_base 3179 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(bank->reg_base); reg_base 437 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg_base; reg_base 444 drivers/pinctrl/samsung/pinctrl-samsung.c pin_to_reg_bank(drvdata, pin - drvdata->pin_base, ®_base, reg_base 458 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg_base + cfg_reg); reg_base 464 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg_base + cfg_reg); reg_base 147 drivers/pinctrl/ti/pinctrl-ti-iodelay.c void __iomem *reg_base; reg_base 857 drivers/pinctrl/ti/pinctrl-ti-iodelay.c iod->reg_base = devm_ioremap_resource(dev, res); reg_base 858 drivers/pinctrl/ti/pinctrl-ti-iodelay.c if (IS_ERR(iod->reg_base)) { reg_base 859 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ret = PTR_ERR(iod->reg_base); reg_base 863 drivers/pinctrl/ti/pinctrl-ti-iodelay.c iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, reg_base 22 drivers/power/supply/goldfish_battery.c void __iomem *reg_base; reg_base 31 drivers/power/supply/goldfish_battery.c (readl(data->reg_base + addr)) reg_base 33 drivers/power/supply/goldfish_battery.c (writel(x, data->reg_base + addr)) reg_base 217 drivers/power/supply/goldfish_battery.c data->reg_base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); reg_base 218 drivers/power/supply/goldfish_battery.c if (data->reg_base == NULL) { reg_base 139 drivers/remoteproc/qcom_q6v5_mss.c void __iomem *reg_base; reg_base 474 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_SLEEP); reg_base 476 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_SLEEP); reg_base 478 drivers/remoteproc/qcom_q6v5_mss.c ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, reg_base 487 drivers/remoteproc/qcom_q6v5_mss.c writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); reg_base 489 drivers/remoteproc/qcom_q6v5_mss.c writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); reg_base 504 drivers/remoteproc/qcom_q6v5_mss.c qproc->reg_base + QDSP6SS_STRAP_ACC); reg_base 507 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); reg_base 509 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); reg_base 512 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); reg_base 514 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); reg_base 517 drivers/remoteproc/qcom_q6v5_mss.c ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, reg_base 526 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 528 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 529 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 534 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 537 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 539 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 543 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 546 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); reg_base 549 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + reg_base 556 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); reg_base 560 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 562 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 565 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); reg_base 567 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); reg_base 570 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 572 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 573 drivers/remoteproc/qcom_q6v5_mss.c val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 579 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 582 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 584 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 586 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 588 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 592 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 595 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); reg_base 597 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); reg_base 600 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); reg_base 602 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); reg_base 605 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_RESET_REG); reg_base 607 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_RESET_REG); reg_base 872 drivers/remoteproc/qcom_q6v5_mss.c val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 875 drivers/remoteproc/qcom_q6v5_mss.c writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); reg_base 1249 drivers/remoteproc/qcom_q6v5_mss.c qproc->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 1250 drivers/remoteproc/qcom_q6v5_mss.c if (IS_ERR(qproc->reg_base)) reg_base 1251 drivers/remoteproc/qcom_q6v5_mss.c return PTR_ERR(qproc->reg_base); reg_base 76 drivers/remoteproc/qcom_q6v5_wcss.c void __iomem *reg_base; reg_base 103 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); reg_base 105 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); reg_base 108 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_XO_CBCR); reg_base 110 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_XO_CBCR); reg_base 113 drivers/remoteproc/qcom_q6v5_wcss.c ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, reg_base 122 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 124 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 129 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 132 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 134 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 138 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 141 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); reg_base 144 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); reg_base 150 drivers/remoteproc/qcom_q6v5_wcss.c val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); reg_base 154 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 156 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 160 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 163 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); reg_base 165 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); reg_base 168 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); reg_base 170 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); reg_base 173 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_RESET_REG); reg_base 175 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_RESET_REG); reg_base 215 drivers/remoteproc/qcom_q6v5_wcss.c writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); reg_base 326 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); reg_base 328 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); reg_base 331 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 333 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 337 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 341 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 345 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 349 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); reg_base 351 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); reg_base 356 drivers/remoteproc/qcom_q6v5_wcss.c val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 358 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 362 drivers/remoteproc/qcom_q6v5_wcss.c writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); reg_base 366 drivers/remoteproc/qcom_q6v5_wcss.c ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, reg_base 471 drivers/remoteproc/qcom_q6v5_wcss.c wcss->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 472 drivers/remoteproc/qcom_q6v5_wcss.c if (IS_ERR(wcss->reg_base)) reg_base 473 drivers/remoteproc/qcom_q6v5_wcss.c return PTR_ERR(wcss->reg_base); reg_base 23 drivers/reset/reset-meson.c void __iomem *reg_base; reg_base 35 drivers/reset/reset-meson.c void __iomem *reg_addr = data->reg_base + (bank << 2); reg_base 49 drivers/reset/reset-meson.c void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2); reg_base 101 drivers/reset/reset-meson.c data->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 102 drivers/reset/reset-meson.c if (IS_ERR(data->reg_base)) reg_base 103 drivers/reset/reset-meson.c return PTR_ERR(data->reg_base); reg_base 58 drivers/rtc/rtc-pic32.c void __iomem *reg_base; reg_base 101 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 119 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 135 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 174 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 194 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 226 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 243 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 267 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; reg_base 315 drivers/rtc/rtc-pic32.c pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 316 drivers/rtc/rtc-pic32.c if (IS_ERR(pdata->reg_base)) reg_base 317 drivers/rtc/rtc-pic32.c return PTR_ERR(pdata->reg_base); reg_base 89 drivers/rtc/rtc-x1205.c unsigned char reg_base) reg_base 91 drivers/rtc/rtc-x1205.c unsigned char dt_addr[2] = { 0, reg_base }; reg_base 123 drivers/rtc/rtc-x1205.c if (reg_base < X1205_CCR_BASE) reg_base 173 drivers/rtc/rtc-x1205.c u8 reg_base, unsigned char alm_enable) reg_base 176 drivers/rtc/rtc-x1205.c unsigned char rdata[10] = { 0, reg_base }; reg_base 209 drivers/rtc/rtc-x1205.c if (reg_base < X1205_CCR_BASE) reg_base 236 drivers/rtc/rtc-x1205.c if (reg_base < X1205_CCR_BASE) { reg_base 44 drivers/rtc/rtc-zynqmp.c void __iomem *reg_base; reg_base 67 drivers/rtc/rtc-zynqmp.c writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); reg_base 69 drivers/rtc/rtc-zynqmp.c writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); reg_base 79 drivers/rtc/rtc-zynqmp.c writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); reg_base 90 drivers/rtc/rtc-zynqmp.c status = readl(xrtcdev->reg_base + RTC_INT_STS); reg_base 97 drivers/rtc/rtc-zynqmp.c rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); reg_base 106 drivers/rtc/rtc-zynqmp.c read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; reg_base 117 drivers/rtc/rtc-zynqmp.c rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); reg_base 118 drivers/rtc/rtc-zynqmp.c alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; reg_base 128 drivers/rtc/rtc-zynqmp.c writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN); reg_base 130 drivers/rtc/rtc-zynqmp.c writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS); reg_base 142 drivers/rtc/rtc-zynqmp.c writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM)); reg_base 154 drivers/rtc/rtc-zynqmp.c rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); reg_base 156 drivers/rtc/rtc-zynqmp.c writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); reg_base 165 drivers/rtc/rtc-zynqmp.c writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); reg_base 181 drivers/rtc/rtc-zynqmp.c status = readl(xrtcdev->reg_base + RTC_INT_STS); reg_base 187 drivers/rtc/rtc-zynqmp.c writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS); reg_base 216 drivers/rtc/rtc-zynqmp.c xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 217 drivers/rtc/rtc-zynqmp.c if (IS_ERR(xrtcdev->reg_base)) reg_base 218 drivers/rtc/rtc-zynqmp.c return PTR_ERR(xrtcdev->reg_base); reg_base 1410 drivers/scsi/bnx2fc/bnx2fc_hwi.c resource_size_t reg_base; reg_base 1414 drivers/scsi/bnx2fc/bnx2fc_hwi.c reg_base = pci_resource_start(hba->pcidev, reg_base 1417 drivers/scsi/bnx2fc/bnx2fc_hwi.c tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); reg_base 405 drivers/scsi/bnx2i/bnx2i.h resource_size_t reg_base; reg_base 2710 drivers/scsi/bnx2i/bnx2i_hwi.c resource_size_t reg_base; reg_base 2715 drivers/scsi/bnx2i/bnx2i_hwi.c reg_base = pci_resource_start(ep->hba->pcidev, reg_base 2718 drivers/scsi/bnx2i/bnx2i_hwi.c ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); reg_base 2739 drivers/scsi/bnx2i/bnx2i_hwi.c ep->qp.ctx_base = ioremap_nocache(ep->hba->reg_base + reg_off, reg_base 817 drivers/scsi/bnx2i/bnx2i_iscsi.c hba->reg_base = pci_resource_start(hba->pcidev, 0); reg_base 35 drivers/soc/amlogic/meson-canvas.c void __iomem *reg_base; reg_base 43 drivers/soc/amlogic/meson-canvas.c writel_relaxed(val, canvas->reg_base + reg); reg_base 48 drivers/soc/amlogic/meson-canvas.c return readl_relaxed(canvas->reg_base + reg); reg_base 178 drivers/soc/amlogic/meson-canvas.c canvas->reg_base = devm_ioremap_resource(dev, res); reg_base 179 drivers/soc/amlogic/meson-canvas.c if (IS_ERR(canvas->reg_base)) reg_base 180 drivers/soc/amlogic/meson-canvas.c return PTR_ERR(canvas->reg_base); reg_base 231 drivers/soc/dove/pmu.c void __iomem *base = gc->reg_base; reg_base 295 drivers/soc/dove/pmu.c gc->reg_base = pmu->pmc_base; reg_base 65 drivers/soc/qcom/spm.c void __iomem *reg_base; reg_base 119 drivers/soc/qcom/spm.c writel_relaxed(val, drv->reg_base + reg_base 133 drivers/soc/qcom/spm.c writel_relaxed(val, drv->reg_base + reg_base 135 drivers/soc/qcom/spm.c ret = readl_relaxed(drv->reg_base + reg_base 146 drivers/soc/qcom/spm.c return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); reg_base 333 drivers/soc/qcom/spm.c drv->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 334 drivers/soc/qcom/spm.c if (IS_ERR(drv->reg_base)) reg_base 335 drivers/soc/qcom/spm.c return PTR_ERR(drv->reg_base); reg_base 344 drivers/soc/qcom/spm.c addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; reg_base 21 drivers/spi/spi-cavium-octeon.c void __iomem *reg_base; reg_base 32 drivers/spi/spi-cavium-octeon.c reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 33 drivers/spi/spi-cavium-octeon.c if (IS_ERR(reg_base)) { reg_base 34 drivers/spi/spi-cavium-octeon.c err = PTR_ERR(reg_base); reg_base 38 drivers/spi/spi-cavium-octeon.c p->register_base = reg_base; reg_base 77 drivers/spi/spi-fsl-cpm.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 97 drivers/spi/spi-fsl-cpm.c mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR); reg_base 104 drivers/spi/spi-fsl-cpm.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 149 drivers/spi/spi-fsl-cpm.c mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB); reg_base 182 drivers/spi/spi-fsl-cpm.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 194 drivers/spi/spi-fsl-cpm.c mpc8xxx_spi_write_reg(®_base->event, events); reg_base 92 drivers/spi/spi-fsl-espi.c void __iomem *reg_base; reg_base 118 drivers/spi/spi-fsl-espi.c return ioread32be(espi->reg_base + offset); reg_base 123 drivers/spi/spi-fsl-espi.c return ioread16be(espi->reg_base + offset); reg_base 128 drivers/spi/spi-fsl-espi.c return ioread8(espi->reg_base + offset); reg_base 134 drivers/spi/spi-fsl-espi.c iowrite32be(val, espi->reg_base + offset); reg_base 140 drivers/spi/spi-fsl-espi.c iowrite16be(val, espi->reg_base + offset); reg_base 146 drivers/spi/spi-fsl-espi.c iowrite8(val, espi->reg_base + offset); reg_base 701 drivers/spi/spi-fsl-espi.c espi->reg_base = devm_ioremap_resource(dev, mem); reg_base 702 drivers/spi/spi-fsl-espi.c if (IS_ERR(espi->reg_base)) { reg_base 703 drivers/spi/spi-fsl-espi.c ret = PTR_ERR(espi->reg_base); reg_base 724 drivers/spi/spi-fsl-espi.c dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq); reg_base 22 drivers/spi/spi-fsl-lib.h void __iomem *reg_base; reg_base 93 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 94 drivers/spi/spi-fsl-spi.c __be32 __iomem *mode = ®_base->mode; reg_base 294 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 299 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); reg_base 303 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->transmit, word); reg_base 312 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base; reg_base 317 drivers/spi/spi-fsl-spi.c reg_base = mpc8xxx_spi->reg_base; reg_base 350 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, 0); reg_base 444 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base; reg_base 460 drivers/spi/spi-fsl-spi.c reg_base = mpc8xxx_spi->reg_base; reg_base 463 drivers/spi/spi-fsl-spi.c cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); reg_base 499 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 503 drivers/spi/spi-fsl-spi.c u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); reg_base 512 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_read_reg(®_base->event)) & reg_base 517 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->event, events); reg_base 523 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->transmit, word); reg_base 534 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mspi->reg_base; reg_base 537 drivers/spi/spi-fsl-spi.c events = mpc8xxx_spi_read_reg(®_base->event); reg_base 554 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; reg_base 561 drivers/spi/spi-fsl-spi.c slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); reg_base 563 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); reg_base 572 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; reg_base 576 drivers/spi/spi-fsl-spi.c capabilities = mpc8xxx_spi_read_reg(®_base->cap); reg_base 586 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); reg_base 598 drivers/spi/spi-fsl-spi.c struct fsl_spi_reg *reg_base; reg_base 625 drivers/spi/spi-fsl-spi.c mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); reg_base 626 drivers/spi/spi-fsl-spi.c if (IS_ERR(mpc8xxx_spi->reg_base)) { reg_base 627 drivers/spi/spi-fsl-spi.c ret = PTR_ERR(mpc8xxx_spi->reg_base); reg_base 653 drivers/spi/spi-fsl-spi.c reg_base = mpc8xxx_spi->reg_base; reg_base 656 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mode, 0); reg_base 657 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, 0); reg_base 658 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->command, 0); reg_base 659 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); reg_base 670 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mode, regval); reg_base 676 drivers/spi/spi-fsl-spi.c dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, reg_base 30 drivers/staging/goldfish/goldfish_audio.c char __iomem *reg_base; reg_base 105 drivers/staging/goldfish/goldfish_audio.c return readl(data->reg_base + addr); reg_base 111 drivers/staging/goldfish/goldfish_audio.c writel(x, data->reg_base + addr); reg_base 117 drivers/staging/goldfish/goldfish_audio.c char __iomem *reg_base = data->reg_base; reg_base 119 drivers/staging/goldfish/goldfish_audio.c gf_write_dma_addr(x, reg_base + addr_lo, reg_base + addr_hi); reg_base 300 drivers/staging/goldfish/goldfish_audio.c data->reg_base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); reg_base 301 drivers/staging/goldfish/goldfish_audio.c if (!data->reg_base) reg_base 153 drivers/staging/media/meson/vdec/vdec_helpers.c u32 reg_base[], u32 reg_num[]) reg_base 159 drivers/staging/media/meson/vdec/vdec_helpers.c u32 reg_cur = reg_base[0]; reg_base 166 drivers/staging/media/meson/vdec/vdec_helpers.c if (!reg_base[reg_base_cur]) reg_base 169 drivers/staging/media/meson/vdec/vdec_helpers.c reg_cur = reg_base[reg_base_cur] + reg_num_cur * 4; reg_base 20 drivers/staging/media/meson/vdec/vdec_helpers.h u32 reg_base[], u32 reg_num[]); reg_base 2081 drivers/staging/qlge/qlge.h void __iomem *reg_base; reg_base 2160 drivers/staging/qlge/qlge.h return readl(qdev->reg_base + reg); reg_base 2168 drivers/staging/qlge/qlge.h writel(val, qdev->reg_base + reg); reg_base 1599 drivers/staging/qlge/qlge_dbg.c DUMP_QDEV_FIELD(qdev, "%p", reg_base); reg_base 4563 drivers/staging/qlge/qlge_main.c if (qdev->reg_base) reg_base 4564 drivers/staging/qlge/qlge_main.c iounmap(qdev->reg_base); reg_base 4619 drivers/staging/qlge/qlge_main.c qdev->reg_base = reg_base 4622 drivers/staging/qlge/qlge_main.c if (!qdev->reg_base) { reg_base 45 drivers/usb/host/ehci-pmcmsp.c struct ehci_regs *reg_base = ehci->regs; reg_base 48 drivers/usb/host/ehci-pmcmsp.c base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; reg_base 49 drivers/usb/host/ehci-pmcmsp.c statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; reg_base 50 drivers/usb/host/ehci-pmcmsp.c fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; reg_base 83 drivers/usb/musb/am35x.c void __iomem *reg_base = musb->ctrl_base; reg_base 90 drivers/usb/musb/am35x.c musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); reg_base 91 drivers/usb/musb/am35x.c musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); reg_base 94 drivers/usb/musb/am35x.c musb_writel(reg_base, CORE_INTR_SRC_SET_REG, reg_base 103 drivers/usb/musb/am35x.c void __iomem *reg_base = musb->ctrl_base; reg_base 105 drivers/usb/musb/am35x.c musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); reg_base 106 drivers/usb/musb/am35x.c musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, reg_base 108 drivers/usb/musb/am35x.c musb_writel(reg_base, USB_END_OF_INTR_REG, 0); reg_base 200 drivers/usb/musb/am35x.c void __iomem *reg_base = musb->ctrl_base; reg_base 211 drivers/usb/musb/am35x.c epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); reg_base 214 drivers/usb/musb/am35x.c musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); reg_base 223 drivers/usb/musb/am35x.c usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); reg_base 228 drivers/usb/musb/am35x.c musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); reg_base 242 drivers/usb/musb/am35x.c int drvvbus = musb_readl(reg_base, USB_STAT_REG); reg_base 301 drivers/usb/musb/am35x.c musb_writel(reg_base, USB_END_OF_INTR_REG, 0); reg_base 333 drivers/usb/musb/am35x.c void __iomem *reg_base = musb->ctrl_base; reg_base 339 drivers/usb/musb/am35x.c rev = musb_readl(reg_base, USB_REVISION_REG); reg_base 354 drivers/usb/musb/am35x.c musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); reg_base 86 drivers/usb/musb/da8xx.c void __iomem *reg_base = musb->ctrl_base; reg_base 93 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); reg_base 96 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, reg_base 105 drivers/usb/musb/da8xx.c void __iomem *reg_base = musb->ctrl_base; reg_base 107 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, reg_base 110 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); reg_base 225 drivers/usb/musb/da8xx.c void __iomem *reg_base = musb->ctrl_base; reg_base 238 drivers/usb/musb/da8xx.c status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); reg_base 242 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); reg_base 258 drivers/usb/musb/da8xx.c int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); reg_base 314 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); reg_base 357 drivers/usb/musb/da8xx.c void __iomem *reg_base = musb->ctrl_base; reg_base 370 drivers/usb/musb/da8xx.c rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); reg_base 383 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); reg_base 402 drivers/usb/musb/da8xx.c musb_readb(reg_base, DA8XX_USB_CTRL_REG)); reg_base 448 drivers/usb/musb/da8xx.c void __iomem *reg_base = musb->ctrl_base; reg_base 450 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); reg_base 173 drivers/usb/musb/musb_dsps.c void __iomem *reg_base = musb->ctrl_base; reg_base 181 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->epintr_set, epmask); reg_base 182 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->coreintr_set, coremask); reg_base 199 drivers/usb/musb/musb_dsps.c void __iomem *reg_base = musb->ctrl_base; reg_base 201 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); reg_base 202 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->epintr_clear, reg_base 317 drivers/usb/musb/musb_dsps.c void __iomem *reg_base = musb->ctrl_base; reg_base 328 drivers/usb/musb/musb_dsps.c epintr = musb_readl(reg_base, wrp->epintr_status); reg_base 333 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->epintr_status, epintr); reg_base 336 drivers/usb/musb/musb_dsps.c usbintr = musb_readl(reg_base, wrp->coreintr_status); reg_base 342 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->coreintr_status, usbintr); reg_base 348 drivers/usb/musb/musb_dsps.c int drvvbus = musb_readl(reg_base, wrp->status); reg_base 431 drivers/usb/musb/musb_dsps.c void __iomem *reg_base; reg_base 437 drivers/usb/musb/musb_dsps.c reg_base = devm_ioremap_resource(dev, r); reg_base 438 drivers/usb/musb/musb_dsps.c if (IS_ERR(reg_base)) reg_base 439 drivers/usb/musb/musb_dsps.c return PTR_ERR(reg_base); reg_base 440 drivers/usb/musb/musb_dsps.c musb->ctrl_base = reg_base; reg_base 450 drivers/usb/musb/musb_dsps.c rev = musb_readl(reg_base, wrp->revision); reg_base 470 drivers/usb/musb/musb_dsps.c musb_writel(reg_base, wrp->control, (1 << wrp->reset)); reg_base 475 drivers/usb/musb/musb_dsps.c val = musb_readl(reg_base, wrp->phy_utmi); reg_base 38 drivers/video/fbdev/goldfishfb.c void __iomem *reg_base; reg_base 55 drivers/video/fbdev/goldfishfb.c status = readl(fb->reg_base + FB_INT_STATUS); reg_base 123 drivers/video/fbdev/goldfishfb.c writel(fb->rotation, fb->reg_base + FB_SET_ROTATION); reg_base 139 drivers/video/fbdev/goldfishfb.c fb->reg_base + FB_SET_BASE); reg_base 154 drivers/video/fbdev/goldfishfb.c writel(1, fb->reg_base + FB_SET_BLANK); reg_base 157 drivers/video/fbdev/goldfishfb.c writel(0, fb->reg_base + FB_SET_BLANK); reg_base 199 drivers/video/fbdev/goldfishfb.c fb->reg_base = ioremap(r->start, PAGE_SIZE); reg_base 200 drivers/video/fbdev/goldfishfb.c if (fb->reg_base == NULL) { reg_base 211 drivers/video/fbdev/goldfishfb.c width = readl(fb->reg_base + FB_GET_WIDTH); reg_base 212 drivers/video/fbdev/goldfishfb.c height = readl(fb->reg_base + FB_GET_HEIGHT); reg_base 229 drivers/video/fbdev/goldfishfb.c fb->fb.var.height = readl(fb->reg_base + FB_GET_PHYS_HEIGHT); reg_base 230 drivers/video/fbdev/goldfishfb.c fb->fb.var.width = readl(fb->reg_base + FB_GET_PHYS_WIDTH); reg_base 262 drivers/video/fbdev/goldfishfb.c writel(FB_INT_BASE_UPDATE_DONE, fb->reg_base + FB_INT_ENABLE); reg_base 279 drivers/video/fbdev/goldfishfb.c iounmap(fb->reg_base); reg_base 297 drivers/video/fbdev/goldfishfb.c iounmap(fb->reg_base); reg_base 35 drivers/video/fbdev/mmp/hw/mmp_ctrl.c isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); reg_base 36 drivers/video/fbdev/mmp/hw/mmp_ctrl.c imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); reg_base 40 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); reg_base 42 drivers/video/fbdev/mmp/hw/mmp_ctrl.c writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); reg_base 43 drivers/video/fbdev/mmp/hw/mmp_ctrl.c } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); reg_base 322 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL); reg_base 324 drivers/video/fbdev/mmp/hw/mmp_ctrl.c writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL); reg_base 330 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); reg_base 333 drivers/video/fbdev/mmp/hw/mmp_ctrl.c writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA); reg_base 488 drivers/video/fbdev/mmp/hw/mmp_ctrl.c ctrl->reg_base = devm_ioremap_nocache(ctrl->dev, reg_base 490 drivers/video/fbdev/mmp/hw/mmp_ctrl.c if (ctrl->reg_base == NULL) { reg_base 1396 drivers/video/fbdev/mmp/hw/mmp_ctrl.h void *reg_base; reg_base 1434 drivers/video/fbdev/mmp/hw/mmp_ctrl.h return path_to_ctrl(path)->reg_base; reg_base 34 drivers/video/fbdev/mmp/hw/mmp_spi.c void *reg_base = reg_base 38 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); reg_base 42 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); reg_base 45 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); reg_base 48 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); reg_base 55 drivers/video/fbdev/mmp/hw/mmp_spi.c tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); reg_base 58 drivers/video/fbdev/mmp/hw/mmp_spi.c writel(tmp, reg_base + LCD_SPU_SPI_CTRL); reg_base 60 drivers/video/fbdev/mmp/hw/mmp_spi.c isr = readl_relaxed(reg_base + SPU_IRQ_ISR); reg_base 63 drivers/video/fbdev/mmp/hw/mmp_spi.c isr = readl_relaxed(reg_base + SPU_IRQ_ISR); reg_base 71 drivers/video/fbdev/mmp/hw/mmp_spi.c tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); reg_base 74 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); reg_base 76 drivers/video/fbdev/mmp/hw/mmp_spi.c writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); reg_base 83 drivers/video/fbdev/mmp/hw/mmp_spi.c void *reg_base = reg_base 91 drivers/video/fbdev/mmp/hw/mmp_spi.c writel(tmp, reg_base + LCD_SPU_SPI_CTRL); reg_base 98 drivers/video/fbdev/mmp/hw/mmp_spi.c tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL); reg_base 102 drivers/video/fbdev/mmp/hw/mmp_spi.c reg_base + SPU_IOPAD_CONTROL); reg_base 149 drivers/video/fbdev/mmp/hw/mmp_spi.c *p_regbase = ctrl->reg_base; reg_base 239 drivers/video/fbdev/mx3fb.c void __iomem *reg_base; reg_base 345 drivers/video/fbdev/mx3fb.c return __raw_readl(mx3fb->reg_base + reg); reg_base 350 drivers/video/fbdev/mx3fb.c __raw_writel(value, mx3fb->reg_base + reg); reg_base 1576 drivers/video/fbdev/mx3fb.c mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); reg_base 1577 drivers/video/fbdev/mx3fb.c if (!mx3fb->reg_base) { reg_base 1582 drivers/video/fbdev/mx3fb.c pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base); reg_base 1616 drivers/video/fbdev/mx3fb.c iounmap(mx3fb->reg_base); reg_base 1637 drivers/video/fbdev/mx3fb.c iounmap(mx3fb->reg_base); reg_base 291 drivers/video/fbdev/pxa168fb.c writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); reg_base 301 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); reg_base 326 drivers/video/fbdev/pxa168fb.c writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); reg_base 338 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); reg_base 348 drivers/video/fbdev/pxa168fb.c writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); reg_base 361 drivers/video/fbdev/pxa168fb.c writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); reg_base 373 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; reg_base 386 drivers/video/fbdev/pxa168fb.c writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); reg_base 399 drivers/video/fbdev/pxa168fb.c writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); reg_base 422 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); reg_base 423 drivers/video/fbdev/pxa168fb.c writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); reg_base 429 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_V_H_ACTIVE); reg_base 446 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH); reg_base 448 drivers/video/fbdev/pxa168fb.c writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); reg_base 450 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_GRA_HPXL_VLN); reg_base 452 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_GZM_HPXL_VLN); reg_base 461 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_H_PORCH); reg_base 463 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_V_PORCH); reg_base 468 drivers/video/fbdev/pxa168fb.c x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); reg_base 469 drivers/video/fbdev/pxa168fb.c writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL); reg_base 508 drivers/video/fbdev/pxa168fb.c writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); reg_base 509 drivers/video/fbdev/pxa168fb.c writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL); reg_base 536 drivers/video/fbdev/pxa168fb.c u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR); reg_base 541 drivers/video/fbdev/pxa168fb.c fbi->reg_base + SPU_IRQ_ISR); reg_base 668 drivers/video/fbdev/pxa168fb.c fbi->reg_base = devm_ioremap_nocache(&pdev->dev, res->start, reg_base 670 drivers/video/fbdev/pxa168fb.c if (fbi->reg_base == NULL) { reg_base 719 drivers/video/fbdev/pxa168fb.c writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR); reg_base 720 drivers/video/fbdev/pxa168fb.c writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL); reg_base 721 drivers/video/fbdev/pxa168fb.c writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1); reg_base 722 drivers/video/fbdev/pxa168fb.c writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN); reg_base 723 drivers/video/fbdev/pxa168fb.c writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0); reg_base 725 drivers/video/fbdev/pxa168fb.c fbi->reg_base + LCD_SPU_SRAM_PARA1); reg_base 749 drivers/video/fbdev/pxa168fb.c writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA); reg_base 789 drivers/video/fbdev/pxa168fb.c data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); reg_base 791 drivers/video/fbdev/pxa168fb.c writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); reg_base 797 drivers/video/fbdev/pxa168fb.c writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); reg_base 1486 drivers/video/fbdev/sm501fb.c static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base) reg_base 1498 drivers/video/fbdev/sm501fb.c par->cursor_regs = info->regs + reg_base; reg_base 33 drivers/watchdog/meson_gxbb_wdt.c void __iomem *reg_base; reg_base 42 drivers/watchdog/meson_gxbb_wdt.c writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN, reg_base 43 drivers/watchdog/meson_gxbb_wdt.c data->reg_base + GXBB_WDT_CTRL_REG); reg_base 52 drivers/watchdog/meson_gxbb_wdt.c writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN, reg_base 53 drivers/watchdog/meson_gxbb_wdt.c data->reg_base + GXBB_WDT_CTRL_REG); reg_base 62 drivers/watchdog/meson_gxbb_wdt.c writel(0, data->reg_base + GXBB_WDT_RSET_REG); reg_base 80 drivers/watchdog/meson_gxbb_wdt.c writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG); reg_base 90 drivers/watchdog/meson_gxbb_wdt.c reg = readl(data->reg_base + GXBB_WDT_TCNT_REG); reg_base 154 drivers/watchdog/meson_gxbb_wdt.c data->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 155 drivers/watchdog/meson_gxbb_wdt.c if (IS_ERR(data->reg_base)) reg_base 156 drivers/watchdog/meson_gxbb_wdt.c return PTR_ERR(data->reg_base); reg_base 185 drivers/watchdog/meson_gxbb_wdt.c data->reg_base + GXBB_WDT_CTRL_REG); reg_base 113 drivers/watchdog/s3c2410_wdt.c void __iomem *reg_base; reg_base 237 drivers/watchdog/s3c2410_wdt.c writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); reg_base 247 drivers/watchdog/s3c2410_wdt.c wtcon = readl(wdt->reg_base + S3C2410_WTCON); reg_base 249 drivers/watchdog/s3c2410_wdt.c writel(wtcon, wdt->reg_base + S3C2410_WTCON); reg_base 272 drivers/watchdog/s3c2410_wdt.c wtcon = readl(wdt->reg_base + S3C2410_WTCON); reg_base 286 drivers/watchdog/s3c2410_wdt.c writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); reg_base 287 drivers/watchdog/s3c2410_wdt.c writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); reg_base 288 drivers/watchdog/s3c2410_wdt.c writel(wtcon, wdt->reg_base + S3C2410_WTCON); reg_base 296 drivers/watchdog/s3c2410_wdt.c return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; reg_base 338 drivers/watchdog/s3c2410_wdt.c wtcon = readl(wdt->reg_base + S3C2410_WTCON); reg_base 342 drivers/watchdog/s3c2410_wdt.c writel(count, wdt->reg_base + S3C2410_WTDAT); reg_base 343 drivers/watchdog/s3c2410_wdt.c writel(wtcon, wdt->reg_base + S3C2410_WTCON); reg_base 354 drivers/watchdog/s3c2410_wdt.c void __iomem *wdt_base = wdt->reg_base; reg_base 408 drivers/watchdog/s3c2410_wdt.c writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); reg_base 547 drivers/watchdog/s3c2410_wdt.c wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 548 drivers/watchdog/s3c2410_wdt.c if (IS_ERR(wdt->reg_base)) { reg_base 549 drivers/watchdog/s3c2410_wdt.c ret = PTR_ERR(wdt->reg_base); reg_base 631 drivers/watchdog/s3c2410_wdt.c wtcon = readl(wdt->reg_base + S3C2410_WTCON); reg_base 688 drivers/watchdog/s3c2410_wdt.c wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); reg_base 689 drivers/watchdog/s3c2410_wdt.c wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); reg_base 707 drivers/watchdog/s3c2410_wdt.c writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); reg_base 708 drivers/watchdog/s3c2410_wdt.c writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ reg_base 709 drivers/watchdog/s3c2410_wdt.c writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); reg_base 30 drivers/watchdog/sama5d4_wdt.c void __iomem *reg_base; reg_base 51 drivers/watchdog/sama5d4_wdt.c readl_relaxed((wdt)->reg_base + (field)) reg_base 65 drivers/watchdog/sama5d4_wdt.c writel_relaxed(val, wdt->reg_base + field); reg_base 73 drivers/watchdog/sama5d4_wdt.c writel_relaxed(val, wdt->reg_base + field); reg_base 225 drivers/watchdog/sama5d4_wdt.c wdt->reg_base = regs; reg_base 50 drivers/watchdog/zx2967_wdt.c void __iomem *reg_base; reg_base 56 drivers/watchdog/zx2967_wdt.c return readl_relaxed(wdt->reg_base + reg); reg_base 61 drivers/watchdog/zx2967_wdt.c writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg); reg_base 215 drivers/watchdog/zx2967_wdt.c wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); reg_base 216 drivers/watchdog/zx2967_wdt.c if (IS_ERR(wdt->reg_base)) reg_base 217 drivers/watchdog/zx2967_wdt.c return PTR_ERR(wdt->reg_base); reg_base 15 include/linux/fpga/altera-pr-ip-core.h int alt_pr_register(struct device *dev, void __iomem *reg_base); reg_base 1009 include/linux/irq.h void __iomem *reg_base; reg_base 1083 include/linux/irq.h void __iomem *reg_base, irq_flow_handler_t handler); reg_base 1093 include/linux/irq.h unsigned int irq_base, void __iomem *reg_base, reg_base 1164 include/linux/irq.h gc->reg_writel(val, gc->reg_base + reg_offset); reg_base 1166 include/linux/irq.h writel(val, gc->reg_base + reg_offset); reg_base 1173 include/linux/irq.h return gc->reg_readl(gc->reg_base + reg_offset); reg_base 1175 include/linux/irq.h return readl(gc->reg_base + reg_offset); reg_base 67 include/video/pxa168fb.h void __iomem *reg_base; reg_base 219 kernel/irq/devres.c unsigned int irq_base, void __iomem *reg_base, reg_base 227 kernel/irq/devres.c irq_base, reg_base, handler); reg_base 216 kernel/irq/generic-chip.c void __iomem *reg_base, irq_flow_handler_t handler) reg_base 221 kernel/irq/generic-chip.c gc->reg_base = reg_base; reg_base 239 kernel/irq/generic-chip.c void __iomem *reg_base, irq_flow_handler_t handler) reg_base 246 kernel/irq/generic-chip.c irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, reg_base 397 kernel/irq/internals.h void __iomem *reg_base, irq_flow_handler_t handler); reg_base 402 kernel/irq/internals.h void __iomem *reg_base, irq_flow_handler_t handler) { } reg_base 96 sound/soc/zte/zx-i2s.c void __iomem *reg_base; reg_base 180 sound/soc/zte/zx-i2s.c val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL); reg_base 216 sound/soc/zte/zx-i2s.c writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL); reg_base 234 sound/soc/zte/zx-i2s.c val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL); reg_base 275 sound/soc/zte/zx-i2s.c writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL); reg_base 294 sound/soc/zte/zx-i2s.c zx_i2s_rx_dma_en(zx_i2s->reg_base, true); reg_base 296 sound/soc/zte/zx-i2s.c zx_i2s_tx_dma_en(zx_i2s->reg_base, true); reg_base 301 sound/soc/zte/zx-i2s.c zx_i2s_rx_en(zx_i2s->reg_base, true); reg_base 303 sound/soc/zte/zx-i2s.c zx_i2s_tx_en(zx_i2s->reg_base, true); reg_base 308 sound/soc/zte/zx-i2s.c zx_i2s_rx_dma_en(zx_i2s->reg_base, false); reg_base 310 sound/soc/zte/zx-i2s.c zx_i2s_tx_dma_en(zx_i2s->reg_base, false); reg_base 315 sound/soc/zte/zx-i2s.c zx_i2s_rx_en(zx_i2s->reg_base, false); reg_base 317 sound/soc/zte/zx-i2s.c zx_i2s_tx_en(zx_i2s->reg_base, false); reg_base 411 sound/soc/zte/zx-i2s.c zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 412 sound/soc/zte/zx-i2s.c if (IS_ERR(zx_i2s->reg_base)) { reg_base 414 sound/soc/zte/zx-i2s.c return PTR_ERR(zx_i2s->reg_base); reg_base 417 sound/soc/zte/zx-i2s.c writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL); reg_base 78 sound/soc/zte/zx-spdif.c void __iomem *reg_base; reg_base 148 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_CTRL); reg_base 176 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_CTRL); reg_base 178 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_VALID_BIT); reg_base 184 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_VALID_BIT); reg_base 187 sound/soc/zte/zx-spdif.c ret = zx_spdif_chanstats(zx_spdif->reg_base, rate); reg_base 218 sound/soc/zte/zx-spdif.c val = readl_relaxed(zx_spdif->reg_base + ZX_FIFOCTRL); reg_base 220 sound/soc/zte/zx-spdif.c writel_relaxed(val, zx_spdif->reg_base + ZX_FIFOCTRL); reg_base 224 sound/soc/zte/zx-spdif.c zx_spdif_cfg_tx(zx_spdif->reg_base, true); reg_base 230 sound/soc/zte/zx-spdif.c zx_spdif_cfg_tx(zx_spdif->reg_base, false); reg_base 323 sound/soc/zte/zx-spdif.c zx_spdif->reg_base = devm_ioremap_resource(&pdev->dev, res); reg_base 324 sound/soc/zte/zx-spdif.c if (IS_ERR(zx_spdif->reg_base)) { reg_base 326 sound/soc/zte/zx-spdif.c return PTR_ERR(zx_spdif->reg_base); reg_base 329 sound/soc/zte/zx-spdif.c zx_spdif_dev_init(zx_spdif->reg_base);