reg5              219 arch/m68k/atari/debug.c 	int clksrc, clkmode, div, reg3, reg5;
reg5              240 arch/m68k/atari/debug.c 	reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */;
reg5              248 arch/m68k/atari/debug.c 	SCC_WRITE(5, reg5);
reg5              258 arch/m68k/atari/debug.c 	SCC_WRITE(5, reg5 | 8);
reg5              311 arch/s390/include/asm/ap.h 	register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
reg5              317 arch/s390/include/asm/ap.h 		: "d" (reg4), "d" (reg5)
reg5              348 arch/s390/include/asm/ap.h 	register unsigned long reg5 asm("5") = (unsigned long) length;
reg5              357 arch/s390/include/asm/ap.h 		  "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
reg5               61 arch/s390/include/asm/page.h 	register unsigned long reg5 asm ("5") = 0xb0001000;
reg5               64 arch/s390/include/asm/page.h 		: "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5)
reg5              587 arch/s390/include/asm/pgtable.h 	register unsigned long reg5 asm("5") = address;
reg5              591 arch/s390/include/asm/pgtable.h 		     : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce)
reg5               43 arch/s390/kernel/cpcmd.c 	register unsigned long reg5 asm ("5") = *rlen;
reg5               50 arch/s390/kernel/cpcmd.c 		: "+d" (reg4), "+d" (reg5)
reg5               52 arch/s390/kernel/cpcmd.c 	*rlen = reg5;
reg5               91 drivers/net/ethernet/8390/8390.h 	unsigned char reg5;		/* Register '5' in a WD8013 */
reg5              204 drivers/net/ethernet/8390/wd.c 		unsigned char reg5 = inb(ioaddr+5);
reg5              213 drivers/net/ethernet/8390/wd.c 		dev->mem_start = ((reg5 & 0x1c) + 0xc0) << 12;
reg5              214 drivers/net/ethernet/8390/wd.c 		dev->irq = (reg5 & 0xe0) == 0xe0 ? 10 : (reg5 >> 5) + 1;
reg5              378 drivers/net/ethernet/8390/wd.c   ei_status.reg5 = ((dev->mem_start>>19) & 0x1f) | NIC16;
reg5              381 drivers/net/ethernet/8390/wd.c 	  outb(ei_status.reg5, ioaddr+WD_CMDREG5);
reg5              420 drivers/net/ethernet/8390/wd.c 		outb(ISA16 | ei_status.reg5, wd_cmdreg+WD_CMDREG5);
reg5              457 drivers/net/ethernet/8390/wd.c 		outb(ei_status.reg5, wd_cmdreg+WD_CMDREG5);
reg5              470 drivers/net/ethernet/8390/wd.c 		outb(ISA16 | ei_status.reg5, wd_cmdreg+WD_CMDREG5);
reg5              472 drivers/net/ethernet/8390/wd.c 		outb(ei_status.reg5, wd_cmdreg+WD_CMDREG5);
reg5              489 drivers/net/ethernet/8390/wd.c 		outb(ei_status.reg5, wd_cmdreg + WD_CMDREG5 );
reg5             1628 drivers/net/ethernet/adaptec/starfire.c 	u16 reg0, reg1, reg4, reg5;
reg5             1644 drivers/net/ethernet/adaptec/starfire.c 			reg5 = mdio_read(dev, np->phys[0], MII_LPA);
reg5             1645 drivers/net/ethernet/adaptec/starfire.c 			if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
reg5             1648 drivers/net/ethernet/adaptec/starfire.c 			} else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
reg5             1651 drivers/net/ethernet/adaptec/starfire.c 			} else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
reg5              628 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5              752 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             5376 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             5549 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             7097 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             7730 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             7822 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             8671 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             8775 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             9385 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             9889 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             10772 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             11405 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5             11523 drivers/net/ethernet/qlogic/qed/qed_hsi.h 	__le32 reg5;
reg5               70 drivers/video/fbdev/valkyriefb.h 	struct vpreg reg5;
reg5              497 include/linux/qed/fcoe_common.h 	__le32 reg5;
reg5              694 sound/soc/codecs/cx2072x.c 	union cx2072x_reg_i2spcm_ctrl_reg5 reg5;
reg5              835 sound/soc/codecs/cx2072x.c 	reg5.r.i2s_pcm_clk_div_chan_en = 0;
reg5              849 sound/soc/codecs/cx2072x.c 		reg5.r.i2s_pcm_clk_div = (u32)div - 1;
reg5              850 sound/soc/codecs/cx2072x.c 		reg5.r.i2s_pcm_clk_div_chan_en = 1;
reg5              860 sound/soc/codecs/cx2072x.c 	regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
reg5              471 sound/soc/codecs/wm8993.c 	u16 reg1, reg4, reg5;
reg5              497 sound/soc/codecs/wm8993.c 	reg5 = snd_soc_component_read32(component, WM8993_FLL_CONTROL_5);
reg5              498 sound/soc/codecs/wm8993.c 	reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
reg5              505 sound/soc/codecs/wm8993.c 		reg5 |= 1;
reg5              509 sound/soc/codecs/wm8993.c 		reg5 |= 2;
reg5              540 sound/soc/codecs/wm8993.c 	reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
reg5              541 sound/soc/codecs/wm8993.c 	reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
reg5              542 sound/soc/codecs/wm8993.c 	snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
reg5              549 sound/soc/codecs/wm9081.c 	u16 reg1, reg4, reg5;
reg5              571 sound/soc/codecs/wm9081.c 	reg5 = snd_soc_component_read32(component, WM9081_FLL_CONTROL_5);
reg5              572 sound/soc/codecs/wm9081.c 	reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
reg5              576 sound/soc/codecs/wm9081.c 		reg5 |= 0x1;
reg5              613 sound/soc/codecs/wm9081.c 	reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
reg5              614 sound/soc/codecs/wm9081.c 	reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
reg5              615 sound/soc/codecs/wm9081.c 	snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);